| /Linux-v5.10/drivers/clk/ingenic/ |
| D | jz4770-cgu.c | 104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
153 .parents = { JZ4770_CLK_PLL0, },
161 .parents = { JZ4770_CLK_PLL0, },
169 .parents = { JZ4770_CLK_PLL0, },
178 .parents = { JZ4770_CLK_PLL0, },
186 .parents = { JZ4770_CLK_PLL0, },
195 .parents = { JZ4770_CLK_PLL0, },
206 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
213 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
[all …]
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| D | jz4780-cgu.c | 294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
344 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
350 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
356 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
[all …]
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| D | x1830-cgu.c | 114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
228 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
235 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
[all …]
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| D | x1000-cgu.c | 186 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
209 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
234 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
242 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
248 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
254 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
261 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
267 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
274 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
280 .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
[all …]
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| D | jz4725b-cgu.c | 56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
90 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
99 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
108 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
117 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
126 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
143 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
151 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
[all …]
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| D | jz4740-cgu.c | 71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
105 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
114 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
123 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
132 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
141 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
157 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
165 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
[all …]
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| /Linux-v5.10/drivers/clk/zynqmp/ |
| D | clkc.c | 24 /* Flags for parents */
67 * @num_parents: Number of parents of clock
98 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member
122 const char * const *parents,
279 * @parents: Name of this clock's parents
280 * @num_parents: Number of parents
286 const char * const *parents, in zynqmp_clk_register_fixed_factor() argument
307 parents[0], in zynqmp_clk_register_fixed_factor()
315 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
318 * @response: Parents of the given clock
[all …]
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| D | clk-zynqmp.h | 37 const char * const *parents,
42 const char * const *parents,
48 const char * const *parents,
53 const char * const *parents,
59 const char * const *parents,
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| D | clk-mux-zynqmp.c | 16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
98 * @parents: Name of this clock's parents
99 * @num_parents: Number of parents
105 const char * const *parents, in zynqmp_clk_register_mux() argument
124 init.parent_names = parents; in zynqmp_clk_register_mux()
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| /Linux-v5.10/drivers/clk/st/ |
| D | clkgen-mux.c | 21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
66 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
67 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
68 pr_err("%s: Failed to get parents (%ld)\n", in st_of_clkgen_mux_setup()
69 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
[all …]
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| D | clk-flexgen.c | 273 const char **parents; in flexgen_get_parents() local
280 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in flexgen_get_parents()
281 if (!parents) in flexgen_get_parents()
284 *num_parents = of_clk_parent_fill(np, parents, nparents); in flexgen_get_parents()
286 return parents; in flexgen_get_parents()
315 const char **parents; in st_of_flexgen_setup() local
333 parents = flexgen_get_parents(np, &num_parents); in st_of_flexgen_setup()
334 if (!parents) { in st_of_flexgen_setup()
387 clk = clk_register_flexgen(clk_name, parents, num_parents, in st_of_flexgen_setup()
396 kfree(parents); in st_of_flexgen_setup()
[all …]
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| /Linux-v5.10/drivers/clk/sunxi/ |
| D | clk-sun8i-mbus.c | 27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
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| D | clk-sun4i-display.c | 19 u8 parents; member
104 const char *parents[4]; in sun4i_a10_display_init() local
123 ret = of_clk_parent_fill(node, parents, data->parents); in sun4i_a10_display_init()
124 if (ret != data->parents) { in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
158 parents, data->parents, in sun4i_a10_display_init()
224 .parents = 4,
242 .parents = 3,
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| /Linux-v5.10/drivers/clk/tegra/ |
| D | clk-bpmp.c | 23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member
35 unsigned int *parents; member
203 request.parent_id = clk->parents[index]; in tegra_bpmp_clk_set_parent()
244 if (clk->parents[i] == response.parent_id) in tegra_bpmp_clk_get_parent()
351 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
392 dev_printk(level, bpmp->dev, " parents: %u\n", info->num_parents); in tegra_bpmp_clk_info_dump()
395 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]); in tegra_bpmp_clk_info_dump()
427 "clock %u has too many parents (%u, max: %u)\n", in tegra_bpmp_probe_clocks()
472 const char **parents; in tegra_bpmp_clk_register() local
483 clk->parents = devm_kcalloc(bpmp->dev, info->num_parents, in tegra_bpmp_clk_register()
[all …]
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| /Linux-v5.10/drivers/clk/imx/ |
| D | clk.h | 120 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
121 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
242 u8 shift, u8 width, const char * const *parents,
265 u8 shift, u8 width, const char * const *parents, in imx_clk_hw_mux_ldb() argument
268 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux_ldb()
440 u8 shift, u8 width, const char * const *parents, in imx_clk_hw_mux() argument
443 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux()
450 u8 width, const char * const *parents, int num_parents) in imx_dev_clk_hw_mux() argument
452 return clk_hw_register_mux(dev, name, parents, num_parents, in imx_dev_clk_hw_mux()
458 u8 shift, u8 width, const char * const *parents, in imx_clk_mux2() argument
[all …]
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| /Linux-v5.10/drivers/clk/pxa/ |
| D | clk-pxa3xx.c | 97 PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
109 PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
119 PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
120 PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
121 PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
122 PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
123 PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
124 PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
127 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \ argument
129 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
[all …]
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| D | clk-pxa27x.c | 132 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ argument
134 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
140 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
141 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
142 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
143 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
144 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
146 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
147 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
149 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
[all …]
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| D | clk-pxa25x.c | 129 PARENTS(clk_pxa25x_memory) = { "run" };
132 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
133 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
134 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
136 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ argument
138 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
150 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
151 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
153 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
154 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
[all …]
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| D | clk-pxa.h | 17 #define PARENTS(name) \ macro
91 * This clock takes it source from 2 possible parents :
119 #define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \ argument
122 .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
129 #define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \ argument
131 PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
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| /Linux-v5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-j721e-wiz.yaml | 51 assigned-clock-parents:
93 assigned-clock-parents:
100 - assigned-clock-parents
139 assigned-clock-parents:
146 - assigned-clock-parents
183 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
192 assigned-clock-parents = <&k3_clks 293 13>;
199 assigned-clock-parents = <&k3_clks 293 0>;
217 assigned-clock-parents = <&k3_clks 292 11>;
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| /Linux-v5.10/drivers/clk/samsung/ |
| D | clk-exynos-clkout.c | 57 struct clk *parents[EXYNOS_CLKOUT_PARENTS]; in exynos_clkout_init() local
74 parents[i] = of_clk_get_by_name(node, name); in exynos_clkout_init()
75 if (IS_ERR(parents[i])) { in exynos_clkout_init()
80 parent_names[i] = __clk_get_name(parents[i]); in exynos_clkout_init()
124 if (!IS_ERR(parents[i])) in exynos_clkout_init()
125 clk_put(parents[i]); in exynos_clkout_init()
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| /Linux-v5.10/drivers/gpu/drm/sun4i/ |
| D | sun8i_hdmi_phy_clk.c | 148 const char *parents[2]; in sun8i_phy_clk_create() local
150 parents[0] = __clk_get_name(phy->clk_pll0); in sun8i_phy_clk_create()
151 if (!parents[0]) in sun8i_phy_clk_create()
155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
156 if (!parents[1]) in sun8i_phy_clk_create()
166 init.parent_names = parents; in sun8i_phy_clk_create()
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| /Linux-v5.10/drivers/clk/ |
| D | clk-conf.c | 20 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
23 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
27 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
124 * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
125 * and sets any specified clock parents and rates. The @clk_supplier argument
127 * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
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| /Linux-v5.10/drivers/clk/renesas/ |
| D | clk-div6.c | 34 * @parents: Array to map from valid parent clocks indices to hardware indices
43 u8 parents[]; member
142 if (clock->parents[i] == hw_index) in cpg_div6_clock_get_parent()
161 hw_index = clock->parents[index]; in cpg_div6_clock_set_parent()
189 * parents, as the parent selection bits are not restored. in cpg_div6_clock_notifier_call()
224 clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL); in cpg_div6_register()
252 pr_err("%s: invalid number of parents for DIV6 clock %s\n", in cpg_div6_register()
258 /* Filter out invalid parents */ in cpg_div6_register()
262 clock->parents[valid_parents] = i; in cpg_div6_register()
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| /Linux-v5.10/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra210-ahub.yaml | 45 assigned-clock-parents:
65 - assigned-clock-parents
83 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
120 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
131 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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