| /Linux-v5.10/arch/nds32/kernel/ |
| D | ex-entry.S | 22 smw.adm $p0, [$sp], $p0, #0x1
29 sethi $p0, hi20(has_fpu)
30 lbsi $p0, [$p0+lo12(has_fpu)]
31 beqz $p0, skip_fucop_ctl
32 mfsr $p0, $FUCOP_CTL
33 smw.adm $p0, [$sp], $p0, #0x1
34 bclr $p0, $p0, #FUCOP_CTL_offCP0EN
35 mtsr $p0, $FUCOP_CTL
67 andi $p0, $r20, #PSW_mskPOM
69 cmovz $fp, $p1, $p0
[all …]
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| D | ex-exit.S | 29 sethi $p0, hi20(has_fpu)
30 lbsi $p0, [$p0+lo12(has_fpu)]
31 beqz $p0, 2f
53 pop $p0
54 cmovn $sp, $p0, $p0
94 lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
95 andi $p0, $p0, #PSW_mskINTL
96 bnez $p0, resume_kernel ! done with iret
139 lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
140 andi $p0, $p0, #PSW_mskINTL
[all …]
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| /Linux-v5.10/arch/hexagon/mm/ |
| D | copy_user_template.S | 19 p0 = cmp.gtu(bytes,#0) define
20 if (!p0.new) jump:nt .Ldone
26 p0 = bitsclr(r3,#7) define
27 if (!p0.new) jump:nt .Loop_not_aligned_8
52 p0 = bitsclr(r4,#7) define
53 if (p0.new) jump:nt .Lalign
56 p0 = bitsclr(r3,#3) define
57 if (!p0.new) jump:nt .Loop_not_aligned_4
82 p0 = bitsclr(r3,#1) define
83 if (!p0.new) jump:nt .Loop_not_aligned
[all …]
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| D | strnlen_user.S | 39 P0 = cmp.eq(mod8,#0); define
42 if (P0.new) jump:t dw_loop; /* fire up the oven */
50 P0 = cmp.eq(tmp1,#0); define
51 if (P0.new) jump:nt exit_found;
57 P0 = cmp.eq(mod8,#0); define
60 if (!P0) jump alignment_loop;
71 P0 = vcmpb.eq(dbuf,dcmp); define
74 tmp1 = P0;
75 P0 = cmp.gtu(end,start); define
80 if (!P0) jump end_check;
[all …]
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| /Linux-v5.10/arch/hexagon/lib/ |
| D | memset.S | 29 p0 = cmp.eq(r2, #0) define
36 if p0 jumpr r31 /* count == 0, so return */
41 p0 = tstbit(r9, #0) define
58 p0 = tstbit(r9, #1) define
60 if !p0 jump 3f /* skip initial byte store */
71 p0 = tstbit(r9, #2) define
73 if !p0 jump 4f /* skip initial half store */
84 p0 = cmp.gtu(r2, #7) define
86 if !p0 jump 5f /* skip initial word store */
91 p0 = cmp.gtu(r2, #11) define
[all …]
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| /Linux-v5.10/arch/x86/include/asm/ |
| D | xor_avx.h | 29 static void xor_avx_2(unsigned long bytes, unsigned long *p0, unsigned long *p1) in xor_avx_2() argument
41 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
43 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
48 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_2()
55 static void xor_avx_3(unsigned long bytes, unsigned long *p0, unsigned long *p1, in xor_avx_3() argument
70 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
72 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
77 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_3()
85 static void xor_avx_4(unsigned long bytes, unsigned long *p0, unsigned long *p1, in xor_avx_4() argument
102 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_4()
[all …]
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| /Linux-v5.10/arch/nds32/lib/ |
| D | memmove.S | 25 slt $p0, $r0, $r1 ! check if $r0 < $r1
26 beqz $p0, do_reverse ! branch if dst > src
34 lmw.bim $p0, [$r1], $p0 ! Read a word from src
36 smw.bim $p0, [$r0], $p0 ! Copy the word to det
49 lmw.adm $p0, [$r1], $p0 ! Read a word from src
51 smw.adm $p0, [$r0], $p0 ! Copy the word to det
59 lb.bi $p0, [$r1], $t0 ! Read a byte from src
61 sb.bi $p0, [$r0], $t0 ! copy the byte to det
|
| D | memset.S | 16 slli $p0, $r1, #8 ! $p0 = 0000ab00
17 or $r1, $r1, $p0 ! $r1 = 0000abab
18 slli $p0, $r1, #16 ! $p0 = abab0000
19 or $r1, $r1, $p0 ! $r1 = abababab
|
| D | clear_user.S | 20 srli $p0, $r1, #2 ! $p0 = number of word to clear
22 beqz $p0, byte_clear ! Only less than a word to clear
25 addi $p0, $p0, #-1 ! Decrease word count
26 bnez $p0, word_clear ! Continue looping to clear all words
|
| /Linux-v5.10/scripts/coccinelle/misc/ |
| D | doubleinit.cocci | 19 position p0,p;
23 struct I s =@p0 { ..., .fld@p = E, ...};
27 position r.p0,p;
31 struct I s =@p0 { ..., .fld@p = E, ...};
34 p0 << r.p0;
41 cocci.print_main(fld,p0)
46 p0 << r.p0;
54 coccilib.report.print_report(p0[0],msg)
|
| /Linux-v5.10/arch/c6x/include/uapi/asm/ |
| D | swab.h | 29 asm(" swap2 .s1 %p0,%P0\n" in __c6x_swab64()
30 "|| swap2 .l1 %P0,%p0\n" in __c6x_swab64()
31 " swap4 .l1 %p0,%p0\n" in __c6x_swab64()
32 " swap4 .l1 %P0,%P0\n" in __c6x_swab64()
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| /Linux-v5.10/arch/hexagon/include/asm/ |
| D | bitops.h | 39 " { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n" in test_and_clear_bit()
41 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_clear_bit()
44 : "r10", "r11", "r12", "p0", "p1", "memory" in test_and_clear_bit()
63 " { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n" in test_and_set_bit()
65 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_set_bit()
68 : "r10", "r11", "r12", "p0", "p1", "memory" in test_and_set_bit()
89 " { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n" in test_and_change_bit()
91 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_change_bit()
94 : "r10", "r11", "r12", "p0", "p1", "memory" in test_and_change_bit()
166 "{P0 = tstbit(%1,%2); if (P0.new) %0 = #1; if (!P0.new) %0 = #0;}\n" in __test_bit()
[all …]
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| D | cmpxchg.h | 32 " memw_locked(%1,P0) = %2;\n" /* store into memory */ in __xchg()
33 " if (!P0) jump 1b;\n" in __xchg()
36 : "memory", "p0" in __xchg()
63 " { P0 = cmp.eq(%0,%2);\n" \
64 " if (!P0.new) jump:nt 2f; }\n" \
65 " memw_locked(%1,p0) = %3;\n" \
66 " if (!P0) jump 1b;\n" \
70 : "memory", "p0" \
|
| D | atomic.h | 21 " memw_locked(%0,p0) = %1;\n" in atomic_set()
22 " if (!P0) jump 1b;\n" in atomic_set()
25 : "memory", "p0", "r6" in atomic_set()
70 " { P0 = cmp.eq(%0,%2);\n" in atomic_cmpxchg()
71 " if (!P0.new) jump:nt 2f; }\n" in atomic_cmpxchg()
72 " memw_locked(%1,P0) = %3;\n" in atomic_cmpxchg()
73 " if (!P0) jump 1b;\n" in atomic_cmpxchg()
77 : "memory", "p0" in atomic_cmpxchg()
|
| /Linux-v5.10/drivers/gpu/drm/omapdrm/ |
| D | tcm.h | 52 struct tcm_pt p0; member
228 slice->p0.y != slice->p1.y && in tcm_slice()
229 (slice->p0.x || (slice->p1.x != slice->tcm->width - 1))) { in tcm_slice()
232 slice->p1.y = (slice->p0.x) ? slice->p0.y : slice->p1.y - 1; in tcm_slice()
234 parent->p0.x = 0; in tcm_slice()
235 parent->p0.y = slice->p1.y + 1; in tcm_slice()
249 area->p0.y <= area->p1.y && in tcm_area_is_valid()
250 /* 1D coordinate relationship + p0.x check */ in tcm_area_is_valid()
252 area->p0.x < area->tcm->width && in tcm_area_is_valid()
253 area->p0.x + area->p0.y * area->tcm->width <= in tcm_area_is_valid()
[all …]
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| D | tcm-sita.c | 171 area->p0.x = pos % tcm->width; in sita_reserve_1d()
172 area->p0.y = pos / tcm->width; in sita_reserve_1d()
193 area->p0.x = pos % tcm->width; in sita_reserve_2d()
194 area->p0.y = pos / tcm->width; in sita_reserve_2d()
195 area->p1.x = area->p0.x + w - 1; in sita_reserve_2d()
196 area->p1.y = area->p0.y + h - 1; in sita_reserve_2d()
213 pos = area->p0.x + area->p0.y * tcm->width; in sita_free()
215 w = area->p1.x - area->p0.x + 1; in sita_free()
216 h = area->p1.y - area->p0.y + 1; in sita_free()
|
| /Linux-v5.10/arch/ia64/lib/ |
| D | memset.S | 69 cmp.eq p_scr, p0 = cnt, r0
81 cmp.ne p_unalgn, p0 = tmp, r0 //
84 cmp.gt p_scr, p0 = 16, cnt // is it a minimalistic task?
118 cmp.gt p_scr, p0 = tmp, cnt // is it a minimalistic task?
137 cmp.gt p_scr, p0 = PREF_AHEAD, linecnt // check against actual value
186 cmp.lt p_scr, p0 = ptr9, ptr1 // do we need more prefetching?
194 cmp.le p_scr, p0 = 8, cnt // just a few bytes left ?
207 cmp.gt p_scr, p0 = PREF_AHEAD, linecnt // check against actual value
240 cmp.lt p_scr, p0 = ptr9, ptr1 // do we need more prefetching?
248 cmp.gt p_scr, p0 = 8, cnt // just a few bytes left ?
[all …]
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| D | memcpy_mck.S | 95 cmp.gt p15,p0=8,in2 // check for small size
96 cmp.ne p13,p0=0,r28 // check dest alignment
97 cmp.ne p14,p0=0,r29 // check src alignment
104 cmp.le p6,p0 = 1,r30 // for .align_dest
119 cmp.lt p6,p0=2*PREFETCH_DIST,cnt
145 cmp.eq p10,p0=r29,r0 // do we really need to loop?
147 cmp.le p6,p0=8,tmp
149 cmp.le p7,p0=16,tmp
174 cmp.le p8,p0=24,tmp
218 cmp.eq p16, p0 = r0, r0 // reset p16 to 1
[all …]
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| D | clear_user.S | 60 cmp.eq p6,p0=r0,len // check for zero length
69 cmp.lt p6,p0=16,len // if len > 16 then long memset
104 tbit.nz p6,p0=buf,0 // odd alignment (for long_do_clear)
108 tbit.nz p6,p0=buf,1
112 tbit.nz p6,p0=buf,2
116 tbit.nz p6,p0=buf,3
122 cmp.eq p6,p0=r0,cnt
167 tbit.nz p6,p0=len,3
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| /Linux-v5.10/Documentation/devicetree/bindings/ata/ |
| D | ahci-ceva.txt | 8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
49 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
50 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
51 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
52 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
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| /Linux-v5.10/drivers/scsi/qla4xxx/ |
| D | ql4_dbg.c | 106 offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf), in qla4xxx_dump_registers()
107 readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); in qla4xxx_dump_registers()
109 offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl), in qla4xxx_dump_registers()
110 readw(&ha->reg->u2.isp4022.p0.port_ctrl)); in qla4xxx_dump_registers()
112 offsetof(struct isp_reg, u2.isp4022.p0.port_status), in qla4xxx_dump_registers()
113 readw(&ha->reg->u2.isp4022.p0.port_status)); in qla4xxx_dump_registers()
115 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out), in qla4xxx_dump_registers()
116 readw(&ha->reg->u2.isp4022.p0.gp_out)); in qla4xxx_dump_registers()
118 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in), in qla4xxx_dump_registers()
119 readw(&ha->reg->u2.isp4022.p0.gp_in)); in qla4xxx_dump_registers()
[all …]
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| /Linux-v5.10/tools/memory-model/Documentation/ |
| D | explanation.txt | 115 P0()
131 Here the P0() function represents the interrupt handler running on one
134 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
162 instance, P1 might run entirely before P0 begins, in which case r1 and
163 r2 will both be 0 at the end. Or P0 might run entirely before P1
167 routines run concurrently. One possibility is that P1 runs after P0's
196 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
202 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
206 P0 stores 1 to buf before storing 1 to flag, since it executes
209 Since an instruction (in this case, P0's store to flag) cannot
[all …]
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| /Linux-v5.10/tools/memory-model/litmus-tests/ |
| D | README | 184 P0(int *x, int *y)
208 P0()'s WRITE_ONCE() is read by its first READ_ONCE(), which is a
209 reads-from link (rf) and internal to the P0() process. This is
215 P0()'s second access is a READ_ONCE(), as opposed to (for example)
218 P0()'s third access is also a READ_ONCE(), but to y rather than x.
219 This is related to P0()'s second access by program order ("po"),
221 The resulting descriptor is "PodRR". Because P0()'s third access is
224 A from-read ("fre") relation links P0()'s third to P1()'s first
229 The remainder of P1() is similar to P0(), which means we add
231 P0()'s first access, which is WRITE_ONCE(), so we add "Fre Once".
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| /Linux-v5.10/arch/ia64/kernel/ |
| D | fsys.S | 89 cmp.ne p8,p0=0,r9
118 cmp.ne p8,p0=0,r9
146 tnat.nz p6,p0 = r33 // guard against NaT argument
195 tnat.nz p6,p0 = r31 // guard against Nat argument
210 cmp.ne p6, p0 = 0, r2 // Fallback if work is scheduled
230 (p8) cmp.ne p13,p0 = r2,r0 // need itc_jitter compensation, set p13
233 (p9) cmp.eq p13,p0 = 0,r30 // if mmio_ptr, clear p13 jitter control
252 (p7) cmp.ne p7,p0 = r25,r3 // if cmpxchg not successful
272 cmp4.ne p7,p0 = r28,r10
283 cmp.ge p6,p0 = r8,r2
[all …]
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| /Linux-v5.10/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1232-revA.dts | 42 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
43 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
44 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
45 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
