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/Linux-v6.1/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Bindings
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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Dallwinner,sun50i-h6-operating-points.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 OPP varies based on the silicon variant in use. Allwinner Process
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
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Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP bindings
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
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Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Binding
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
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/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-s922x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <731000>;
19 opp-1200000000 {
20 opp-hz = /bits/ 64 <1200000000>;
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Dmeson-g12b-a311d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <761000>;
19 opp-1200000000 {
20 opp-hz = /bits/ 64 <1200000000>;
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Dmeson-g12a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
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/Linux-v6.1/arch/arm/boot/dts/
Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
32 #address-cells = <1>;
33 #size-cells = <0>;
35 cpu-map {
48 compatible = "arm,cortex-a9";
51 clock-names = "cpu";
52 clock-latency = <160000>;
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Drk3229.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /delete-node/ opp-table0;
13 cpu0_opp_table: opp-table-0 {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-408000000 {
18 opp-hz = /bits/ 64 <408000000>;
19 opp-microvolt = <950000>;
20 clock-latency-ns = <40000>;
21 opp-suspend;
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Dsun8i-r40-cpu-opp.dtsi2 cpu0_opp_table: opp-table-cpu {
3 compatible = "operating-points-v2";
4 opp-shared;
6 opp-720000000 {
7 opp-hz = /bits/ 64 <720000000>;
8 opp-microvolt = <1000000 1000000 1300000>;
9 clock-latency-ns = <2000000>;
12 opp-912000000 {
13 opp-hz = /bits/ 64 <912000000>;
14 opp-microvolt = <1100000 1100000 1300000>;
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Dmstar-infinity.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "mstar-v7.dtsi"
9 #include <dt-bindings/gpio/msc313-gpio.h>
13 compatible = "operating-points-v2";
14 opp-shared;
16 opp-240000000 {
17 opp-hz = /bits/ 64 <240000000>;
18 opp-microvolt = <1000000>;
19 clock-latency-ns = <300000>;
22 opp-400000000 {
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/Linux-v6.1/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3399-t-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
8 cluster0_opp: opp-table-0 {
9 compatible = "operating-points-v2";
10 opp-shared;
13 opp-hz = /bits/ 64 <408000000>;
14 opp-microvolt = <875000 875000 1250000>;
15 clock-latency-ns = <40000>;
18 opp-hz = /bits/ 64 <600000000>;
19 opp-microvolt = <875000 875000 1250000>;
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Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table-0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <825000 825000 1250000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000 825000 1250000>;
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Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table-0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsa8540p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ &cpu0_opp_table;
10 /delete-node/ &cpu4_opp_table;
13 cpu0_opp_table: cpu0-opp-table {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-403200000 {
18 opp-hz = /bits/ 64 <403200000>;
20 opp-499200000 {
21 opp-hz = /bits/ 64 <499200000>;
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/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
30 operating-points-v2 = <&bus_gscl_opp_table>;
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/Linux-v6.1/drivers/opp/
Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP helper interface for CPU device
5 * Copyright (C) 2009-2014 Texas Instruments Incorporated.
20 #include "opp.h"
25 * dev_pm_opp_init_cpufreq_table() - create a cpufreq table for a device
29 * Generate a cpufreq table for a provided device- this assumes that the
30 * opp table is already initialized and ready for usage.
36 * Returns -EINVAL for bad pointers, -ENODEV if the device is not found, -ENOMEM
46 struct dev_pm_opp *opp; in dev_pm_opp_init_cpufreq_table() local
53 return max_opps ? max_opps : -ENODATA; in dev_pm_opp_init_cpufreq_table()
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Dopp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
26 /* Lock to allow exclusive modification to the device and opp lists */
31 /* OPP Config flags */
40 * struct opp_config_data - data for set config operations
41 * @opp_table: OPP table
42 * @flags: OPP config flags
44 * This structure stores the OPP config information for each OPP table
53 * Internal data structure organization with the OPP layer library is as
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/Linux-v6.1/drivers/cpufreq/
Dscmi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2021 ARM Ltd.
11 #include <linux/clk-provider.h>
37 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_get_rate()
41 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
48 * perf_ops->freq_set is not a synchronous, the actual OPP change will
55 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
56 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target()
58 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
64 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
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Dcpufreq-dt.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "cpufreq-dt.h"
41 NULL, /* Extra space for boost-attr if required */
50 if (cpumask_test_cpu(cpu, priv->cpus)) in cpufreq_dt_find_data()
59 struct private_data *priv = policy->driver_data; in set_target()
60 unsigned long freq = policy->freq_table[index].frequency; in set_target()
62 return dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); in set_target()
66 * An earlier version of opp-v1 bindings used to name the regulator
67 * "cpu0-supply", we still need to handle that for backwards compatibility.
73 int cpu = dev->id; in find_supply_name()
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/Linux-v6.1/arch/arm64/boot/dts/allwinner/
Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 cpu0_opp_table: opp-table-cpu {
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
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Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: opp-table-cpu {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
[all …]
Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: opp-table-cpu {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
11 opp-480000000 {
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
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/Linux-v6.1/Documentation/devicetree/bindings/interconnect/
Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
26 - description:
28 - description:
33 clock-names:
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