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/Linux-v5.15/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Bindings
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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Dallwinner,sun50i-h6-operating-points.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 OPP varies based on the silicon variant in use. Allwinner Process
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
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Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Binding
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
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Dqcom-nvmem-cpufreq.txt1 Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
5 the CPU frequencies subset and voltage value of each OPP varies based on
8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
11 to provide the OPP framework with required information (existing HW bitmap).
12 This is used to determine the voltage and frequency value for each OPP of
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
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/Linux-v5.15/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
20 The parent bus device can only change the voltage of shared power line
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
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/Linux-v5.15/arch/arm/boot/dts/
Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
32 #address-cells = <1>;
33 #size-cells = <0>;
35 cpu-map {
48 compatible = "arm,cortex-a9";
51 clock-names = "cpu";
52 clock-latency = <160000>;
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Drk3229.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /delete-node/ opp-table0;
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-408000000 {
18 opp-hz = /bits/ 64 <408000000>;
19 opp-microvolt = <950000>;
20 clock-latency-ns = <40000>;
21 opp-suspend;
23 opp-600000000 {
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Dstih418-b2264.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2264", "st,stih418";
14 stdout-path = &sbc_serial0;
24 operating-points-v2 = <&cpu_opp_table>;
25 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
26 cpu-release-addr = <0x94100b8>;
29 operating-points-v2 = <&cpu_opp_table>;
30 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
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Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp@216000000,750 {
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
12 opp-suspend;
15 opp@216000000,800 {
16 clock-latency-ns = <400000>;
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/Linux-v5.15/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-s922x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-100000000 {
15 opp-hz = /bits/ 64 <100000000>;
16 opp-microvolt = <731000>;
19 opp-250000000 {
20 opp-hz = /bits/ 64 <250000000>;
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Dmeson-g12b-a311d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-100000000 {
15 opp-hz = /bits/ 64 <100000000>;
16 opp-microvolt = <731000>;
19 opp-250000000 {
20 opp-hz = /bits/ 64 <250000000>;
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Dmeson-g12a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
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/Linux-v5.15/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
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/Linux-v5.15/arch/arm64/boot/dts/rockchip/
Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
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Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <825000 825000 1250000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000 825000 1250000>;
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/Linux-v5.15/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
30 operating-points-v2 = <&bus_gscl_opp_table>;
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/Linux-v5.15/drivers/opp/
Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP helper interface for CPU device
5 * Copyright (C) 2009-2014 Texas Instruments Incorporated.
20 #include "opp.h"
25 * dev_pm_opp_init_cpufreq_table() - create a cpufreq table for a device
29 * Generate a cpufreq table for a provided device- this assumes that the
30 * opp table is already initialized and ready for usage.
36 * Returns -EINVAL for bad pointers, -ENODEV if the device is not found, -ENOMEM
46 struct dev_pm_opp *opp; in dev_pm_opp_init_cpufreq_table() local
53 return max_opps ? max_opps : -ENODATA; in dev_pm_opp_init_cpufreq_table()
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Dopp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
26 /* Lock to allow exclusive modification to the device and opp lists */
32 * Internal data structure organization with the OPP layer library is as
35 * |- device 1 (represents voltage domain 1)
36 * | |- opp 1 (availability, freq, voltage)
37 * | |- opp 2 ..
39 * | `- opp n ..
40 * |- device 2 (represents the next voltage domain)
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Dof.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP OF helpers
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
22 #include "opp.h"
25 * Returns opp descriptor node for a device node, caller must
31 /* "operating-points-v2" can be an array for power domain providers */ in _opp_of_get_opp_desc_node()
32 return of_parse_phandle(np, "operating-points-v2", index); in _opp_of_get_opp_desc_node()
35 /* Returns opp descriptor node for a device, caller must do of_node_put() */
38 return _opp_of_get_opp_desc_node(dev->of_node, 0); in dev_pm_opp_of_get_opp_desc_node()
47 np = _opp_of_get_opp_desc_node(dev->of_node, index); in _managed_opp()
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Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP debugfs interface
5 * Copyright (C) 2015-2016 Viresh Kumar <viresh.kumar@linaro.org>
17 #include "opp.h"
23 if (dev->parent) in opp_set_dev_name()
24 snprintf(name, NAME_MAX, "%s-%s", dev_name(dev->parent), in opp_set_dev_name()
30 void opp_debug_remove_one(struct dev_pm_opp *opp) in opp_debug_remove_one() argument
32 debugfs_remove_recursive(opp->dentry); in opp_debug_remove_one()
38 struct icc_path *path = fp->private_data; in bw_name_read()
53 static void opp_debug_create_bw(struct dev_pm_opp *opp, in opp_debug_create_bw() argument
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/Linux-v5.15/drivers/cpufreq/
Dscmi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2021 ARM Ltd.
11 #include <linux/clk-provider.h>
36 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_get_rate()
40 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
47 * perf_ops->freq_set is not a synchronous, the actual OPP change will
54 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
55 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target()
57 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
63 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
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Dcpufreq-dt.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "cpufreq-dt.h"
41 NULL, /* Extra space for boost-attr if required */
50 if (cpumask_test_cpu(cpu, priv->cpus)) in cpufreq_dt_find_data()
59 struct private_data *priv = policy->driver_data; in set_target()
60 unsigned long freq = policy->freq_table[index].frequency; in set_target()
62 return dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); in set_target()
66 * An earlier version of opp-v1 bindings used to name the regulator
67 * "cpu0-supply", we still need to handle that for backwards compatibility.
73 int cpu = dev->id; in find_supply_name()
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/Linux-v5.15/arch/arm64/boot/dts/allwinner/
Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
19 opp-microvolt = <1100000>;
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Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: cpu-opp-table {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
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Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: cpu-opp-table {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
11 opp-480000000 {
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
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