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/Linux-v6.1/Documentation/devicetree/bindings/opp/
Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm OPP bindings to describe OPP nodes.
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
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/Linux-v6.1/Documentation/devicetree/bindings/power/avs/
Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
14 or other device. Each OPP of a device corresponds to a "corner" that has
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
36 - description: Reference clock.
38 clock-names:
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/Linux-v6.1/Documentation/devicetree/bindings/cpufreq/
Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
25 - qcom,apq8064
26 - qcom,apq8096
27 - qcom,ipq8064
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/Linux-v6.1/drivers/soc/qcom/
Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
125 #define FUSE_REVISION_UNKNOWN (-1)
146 /* fuse quot */
150 /* fuse quot_offset */
254 return !drv->loop_disabled; in cpr_is_allowed()
259 writel_relaxed(value, drv->base + offset); in cpr_write()
264 return readl_relaxed(drv->base + offset); in cpr_read()
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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dqcs404.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
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/Linux-v6.1/drivers/memory/tegra/
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
29 #include <soc/tegra/fuse.h>
221 /* protect shared rate-change code path */
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
264 timing = &emc->timings[i]; in tegra_emc_find_timing()
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Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
26 #include <soc/tegra/fuse.h>
512 /* protect shared rate-change code path */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
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Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
33 #include <soc/tegra/fuse.h>
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
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/Linux-v6.1/arch/arm/boot/dts/
Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
43 stdout-path = "serial0:115200n8";
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Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
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Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
13 interrupt-parent = <&lic>;
14 #address-cells = <1>;
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/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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/Linux-v6.1/drivers/soc/tegra/
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
51 #include <soc/tegra/fuse.h>
54 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 #include "opp.h"
192 init_data->num_virtual_links, dc); in dc_create_resource_pool()
196 init_data->num_virtual_links, dc); in dc_create_resource_pool()
200 init_data->num_virtual_links, dc); in dc_create_resource_pool()
205 init_data->num_virtual_links, dc); in dc_create_resource_pool()
209 init_data->num_virtual_links, dc); in dc_create_resource_pool()
213 init_data->num_virtual_links, dc); in dc_create_resource_pool()
217 init_data->num_virtual_links, dc); in dc_create_resource_pool()
221 init_data->num_virtual_links, dc, in dc_create_resource_pool()
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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