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12

/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
30 operating-points-v2 = <&bus_gscl_opp_table>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dexynos5800.dtsi1 // SPDX-License-Identifier: GPL-2.0
20 compatible = "samsung,exynos5800-clock", "syscon";
24 opp-2000000000 {
25 opp-hz = /bits/ 64 <2000000000>;
26 opp-microvolt = <1312500 1312500 1500000>;
27 clock-latency-ns = <140000>;
29 opp-1900000000 {
30 opp-hz = /bits/ 64 <1900000000>;
31 opp-microvolt = <1262500 1262500 1500000>;
32 clock-latency-ns = <140000>;
[all …]
Dmstar-infinity.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "mstar-v7.dtsi"
9 #include <dt-bindings/gpio/msc313-gpio.h>
13 compatible = "operating-points-v2";
14 opp-shared;
16 opp-240000000 {
17 opp-hz = /bits/ 64 <240000000>;
18 opp-microvolt = <1000000>;
19 clock-latency-ns = <300000>;
22 opp-400000000 {
[all …]
Dtegra30-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1350000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1350000>;
15 opp-level = <1000000>;
[all …]
Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
38 cpu-map {
57 compatible = "arm,cortex-a9";
60 clock-names = "cpu";
61 operating-points-v2 = <&cpu0_opp_table>;
[all …]
Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
Dtegra20-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1300000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1300000>;
15 opp-level = <1000000>;
[all …]
Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
32 #address-cells = <1>;
33 #size-cells = <0>;
35 cpu-map {
48 compatible = "arm,cortex-a9";
51 clock-names = "cpu";
52 clock-latency = <160000>;
[all …]
Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
50 #address-cells = <1>;
51 #size-cells = <0>;
53 cpu-map {
66 compatible = "arm,cortex-a15";
69 clock-names = "cpu";
70 operating-points-v2 = <&cpu0_opp_table>;
[all …]
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
[all …]
Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-gx-mali450.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 gpu_opp_table: opp-table {
9 compatible = "operating-points-v2";
11 opp-125000000 {
12 opp-hz = /bits/ 64 <125000000>;
13 opp-microvolt = <950000>;
15 opp-250000000 {
16 opp-hz = /bits/ 64 <250000000>;
17 opp-microvolt = <950000>;
19 opp-285714285 {
[all …]
Dmeson-gxm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
46 capacity-dmips-mhz = <1024>;
50 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
58 capacity-dmips-mhz = <1024>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table-0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
[all …]
Drk3399-t-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
8 cluster0_opp: opp-table-0 {
9 compatible = "operating-points-v2";
10 opp-shared;
13 opp-hz = /bits/ 64 <408000000>;
14 opp-microvolt = <875000 875000 1250000>;
15 clock-latency-ns = <40000>;
18 opp-hz = /bits/ 64 <600000000>;
19 opp-microvolt = <875000 875000 1250000>;
[all …]
Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table-0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <825000 825000 1250000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000 825000 1250000>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpu/
Darm,mali-midgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
17 - items:
18 - enum:
19 - samsung,exynos5250-mali
20 - const: arm,mali-t604
[all …]
Darm,mali-bifrost.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
18 - items:
19 - enum:
20 - amlogic,meson-g12a-mali
21 - mediatek,mt8183-mali
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mm-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2019-2020 NXP
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include "imx8mm-evk.dtsi"
13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
21 operating-points-v2 = <&ddrc_opp_table>;
23 ddrc_opp_table: opp-table {
24 compatible = "operating-points-v2";
26 opp-25M {
[all …]
Dimx8mq-nitrogen-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
14 stdout-path = &uart1;
17 reg_1p8v: regulator-fixed-1v8 {
18 compatible = "regulator-fixed";
19 regulator-name = "1P8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
24 reg_snvs: regulator-fixed-snvs {
25 compatible = "regulator-fixed";
[all …]
Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
Dimx8mm-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MM";
12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
24 reg_vdd_3v3_s: regulator-vdd-3v3-s {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]

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