Searched full:openrisc (Results 1 – 25 of 140) sorted by relevance
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2 OpenRISC Linux5 This is a port of Linux to the OpenRISC class of microprocessors; the initial6 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).8 For information about OpenRISC processors and ongoing development:11 website https://openrisc.io12 email openrisc@lists.librecores.org17 Build instructions for OpenRISC toolchain and Linux20 In order to build and run Linux for OpenRISC, you'll need at least a basic26 Toolchain binaries can be obtained from openrisc.io or our github releases page.27 Instructions for building the different toolchains can be found on openrisc.io[all …]
3 :Original: Documentation/arch/openrisc/openrisc_port.rst12 OpenRISC Linux16 OpenRISC 1000系列（或1k）。21 网站 https://openrisc.io22 邮箱 openrisc@lists.librecores.org30 为了构建和运行Linux for OpenRISC，你至少需要一个基本的工具链，或许40 二进制 https://github.com/openrisc/or1k-gcc/releases41 工具链 https://openrisc.io/software49 make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig50 make ARCH=openrisc CROSS_COMPILE="or1k-linux-"[all …]
3 :Original: Documentation/arch/openrisc/todo.rst15 OpenRISC Linux的移植已经完全投入使用，并且从 2.6.35 开始就一直在上游同步。
5 :Original: Documentation/arch/openrisc/index.rst14 OpenRISC 体系架构
3 * OpenRISC Linux9 * OpenRISC implementation:22 * PCI: We do not use IO ports in OpenRISC26 /* OpenRISC has no port IO */
3 * OpenRISC Linux9 * OpenRISC implementation:19 * OpenRISC doesn't have an efficient flush_tlb_range() so use flush_tlb_mm()
3 * OpenRISC Linux9 * OpenRISC implementation:33 extern volatile pgd_t *current_pgd[]; /* defined in arch/openrisc/mm/fault.c */
3 * OpenRISC Linux9 * OpenRISC implementation:30 * On OpenRISC we use these special fixed_addresses for doing ioremap
3 * OpenRISC Linux9 * OpenRISC implementation:
3 * OpenRISC Linux9 * OpenRISC implementation:111 /* For OpenRISC, this is anything in the LSW other than syscall trace */
7 config OPENRISC config76 Generic OpenRISC 1200 architecture86 caches at relevant times. Most OpenRISC implementations support write-199 OpenRISC architecture makes it optional to have it implemented202 Say N here if you know that your OpenRISC processor has209 Say Y here if your OpenRISC processor features shadowed
1 OpenRISC Generic SoC4 Boards and FPGA SoC's which support the OpenRISC standard platform. The5 platform essentially follows the conventions of the OpenRISC architecture
3 * OpenRISC cache.c9 * Modifications for the OpenRISC architecture:50 * Since icaches do not snoop for updated data on OpenRISC, we in update_cache()
3 * OpenRISC vmlinux.lds.S9 * Modifications for the OpenRISC architecture:13 * ld script for OpenRISC architecture
3 * OpenRISC time.c9 * Modifications for the OpenRISC architecture:135 * Clocksource: Based on OpenRISC timer/counter137 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
3 * OpenRISC setup.c9 * Modifications for the OpenRISC architecture:107 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", in print_cpuinfo()289 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n"); in setup_arch()310 "OpenRISC 1000 (%d.%d-rev%d)\n", in show_cpuinfo()319 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version); in show_cpuinfo()
3 * OpenRISC sys_call_table.c9 * Modifications for the OpenRISC architecture:
3 * OpenRISC prom.c9 * Modifications for the OpenRISC architecture:
