Searched full:openrisc (Results 1 – 25 of 132) sorted by relevance
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/Linux-v5.4/Documentation/openrisc/ |
D | openrisc_port.rst | 2 OpenRISC Linux 5 This is a port of Linux to the OpenRISC class of microprocessors; the initial 6 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). 8 For information about OpenRISC processors and ongoing development: 11 website http://openrisc.io 12 email openrisc@lists.librecores.org 17 Build instructions for OpenRISC toolchain and Linux 20 In order to build and run Linux for OpenRISC, you'll need at least a basic 26 Toolchain binaries can be obtained from openrisc.io or our github releases page. 27 Instructions for building the different toolchains can be found on openrisc.io [all …]
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/Linux-v5.4/arch/openrisc/ |
D | Makefile | 13 # Modifications for the OpenRISC architecture: 39 head-y := arch/openrisc/kernel/head.o 41 core-y += arch/openrisc/lib/ \ 42 arch/openrisc/kernel/ \ 43 arch/openrisc/mm/ 51 core-$(BUILTIN_DTB) += arch/openrisc/boot/dts/
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D | Kconfig | 7 config OPENRISC config 76 Generic OpenRISC 1200 architecture 86 caches at relevant times. Most OpenRISC implementations support write- 146 OpenRISC architecture makes it optional to have it implemented 149 Say N here if you know that your OpenRISC processor has 156 Say Y here if your OpenRISC processor features shadowed
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/Linux-v5.4/arch/openrisc/include/asm/ |
D | tlb.h | 3 * OpenRISC Linux 9 * OpenRISC implementation: 19 * OpenRISC doesn't have an efficient flush_tlb_range() so use flush_tlb_mm()
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D | io.h | 3 * OpenRISC Linux 9 * OpenRISC implementation: 22 /* OpenRISC has no port IO */
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D | mmu_context.h | 3 * OpenRISC Linux 9 * OpenRISC implementation: 33 extern volatile pgd_t *current_pgd[]; /* defined in arch/openrisc/mm/fault.c */
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D | fixmap.h | 3 * OpenRISC Linux 9 * OpenRISC implementation: 30 * On OpenRISC we use these special fixed_addresses for doing ioremap
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D | delay.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | mmu.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | linkage.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | irq.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | irqflags.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | cache.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | cpuinfo.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | timex.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | spinlock.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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D | syscalls.h | 3 * OpenRISC Linux 9 * OpenRISC implementation:
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/Linux-v5.4/Documentation/devicetree/bindings/openrisc/opencores/ |
D | or1ksim.txt | 1 OpenRISC Generic SoC 4 Boards and FPGA SoC's which support the OpenRISC standard platform. The 5 platform essentially follows the conventions of the OpenRISC architecture
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/Linux-v5.4/arch/openrisc/mm/ |
D | cache.c | 3 * OpenRISC cache.c 9 * Modifications for the OpenRISC architecture: 50 * Since icaches do not snoop for updated data on OpenRISC, we in update_cache()
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/Linux-v5.4/arch/openrisc/kernel/ |
D | time.c | 3 * OpenRISC time.c 9 * Modifications for the OpenRISC architecture: 131 * Clocksource: Based on OpenRISC timer/counter 133 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
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D | vmlinux.lds.S | 3 * OpenRISC vmlinux.lds.S 9 * Modifications for the OpenRISC architecture: 13 * ld script for OpenRISC architecture
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D | setup.c | 3 * OpenRISC setup.c 9 * Modifications for the OpenRISC architecture: 103 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", in print_cpuinfo() 318 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n"); in setup_arch() 339 "OpenRISC 1000 (%d.%d-rev%d)\n", in show_cpuinfo() 348 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version); in show_cpuinfo()
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D | sys_call_table.c | 3 * OpenRISC sys_call_table.c 9 * Modifications for the OpenRISC architecture:
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D | prom.c | 3 * OpenRISC prom.c 9 * Modifications for the OpenRISC architecture:
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/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/ |
D | openrisc,ompic.txt | 5 - compatible : This should be "openrisc,ompic" 17 compatible = "openrisc,ompic";
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