Home
last modified time | relevance | path

Searched full:openrisc (Results 1 – 25 of 132) sorted by relevance

123456

/Linux-v5.4/Documentation/openrisc/
Dopenrisc_port.rst2 OpenRISC Linux
5 This is a port of Linux to the OpenRISC class of microprocessors; the initial
6 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
8 For information about OpenRISC processors and ongoing development:
11 website http://openrisc.io
12 email openrisc@lists.librecores.org
17 Build instructions for OpenRISC toolchain and Linux
20 In order to build and run Linux for OpenRISC, you'll need at least a basic
26 Toolchain binaries can be obtained from openrisc.io or our github releases page.
27 Instructions for building the different toolchains can be found on openrisc.io
[all …]
/Linux-v5.4/arch/openrisc/
DMakefile13 # Modifications for the OpenRISC architecture:
39 head-y := arch/openrisc/kernel/head.o
41 core-y += arch/openrisc/lib/ \
42 arch/openrisc/kernel/ \
43 arch/openrisc/mm/
51 core-$(BUILTIN_DTB) += arch/openrisc/boot/dts/
DKconfig7 config OPENRISC config
76 Generic OpenRISC 1200 architecture
86 caches at relevant times. Most OpenRISC implementations support write-
146 OpenRISC architecture makes it optional to have it implemented
149 Say N here if you know that your OpenRISC processor has
156 Say Y here if your OpenRISC processor features shadowed
/Linux-v5.4/arch/openrisc/include/asm/
Dtlb.h3 * OpenRISC Linux
9 * OpenRISC implementation:
19 * OpenRISC doesn't have an efficient flush_tlb_range() so use flush_tlb_mm()
Dio.h3 * OpenRISC Linux
9 * OpenRISC implementation:
22 /* OpenRISC has no port IO */
Dmmu_context.h3 * OpenRISC Linux
9 * OpenRISC implementation:
33 extern volatile pgd_t *current_pgd[]; /* defined in arch/openrisc/mm/fault.c */
Dfixmap.h3 * OpenRISC Linux
9 * OpenRISC implementation:
30 * On OpenRISC we use these special fixed_addresses for doing ioremap
Ddelay.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dmmu.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dlinkage.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dirq.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dirqflags.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dcache.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dcpuinfo.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dtimex.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dspinlock.h3 * OpenRISC Linux
9 * OpenRISC implementation:
Dsyscalls.h3 * OpenRISC Linux
9 * OpenRISC implementation:
/Linux-v5.4/Documentation/devicetree/bindings/openrisc/opencores/
Dor1ksim.txt1 OpenRISC Generic SoC
4 Boards and FPGA SoC's which support the OpenRISC standard platform. The
5 platform essentially follows the conventions of the OpenRISC architecture
/Linux-v5.4/arch/openrisc/mm/
Dcache.c3 * OpenRISC cache.c
9 * Modifications for the OpenRISC architecture:
50 * Since icaches do not snoop for updated data on OpenRISC, we in update_cache()
/Linux-v5.4/arch/openrisc/kernel/
Dtime.c3 * OpenRISC time.c
9 * Modifications for the OpenRISC architecture:
131 * Clocksource: Based on OpenRISC timer/counter
133 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
Dvmlinux.lds.S3 * OpenRISC vmlinux.lds.S
9 * Modifications for the OpenRISC architecture:
13 * ld script for OpenRISC architecture
Dsetup.c3 * OpenRISC setup.c
9 * Modifications for the OpenRISC architecture:
103 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", in print_cpuinfo()
318 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n"); in setup_arch()
339 "OpenRISC 1000 (%d.%d-rev%d)\n", in show_cpuinfo()
348 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version); in show_cpuinfo()
Dsys_call_table.c3 * OpenRISC sys_call_table.c
9 * Modifications for the OpenRISC architecture:
Dprom.c3 * OpenRISC prom.c
9 * Modifications for the OpenRISC architecture:
/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/
Dopenrisc,ompic.txt5 - compatible : This should be "openrisc,ompic"
17 compatible = "openrisc,ompic";

123456