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/Linux-v5.15/arch/arm/boot/dts/
Domap3-devkit8000.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include "omap3-devkit8000-common.dtsi"
10 compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
25 /delete-property/ti,no-reset-on-init;
26 /delete-property/ti,no-idle;
28 /delete-property/ti,timer-alwon;
32 /* Preferred always-on timer for clocksource */
34 ti,no-reset-on-init;
35 ti,no-idle;
[all …]
Domap3-sniper.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015-2016 Paul Kocialkowski <contact@paulk.fr>
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
12 compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3";
16 cpu0-supply = <&vcc>;
27 pinctrl-names = "default";
30 pinctrl-single,pins = <
37 pinctrl-single,pins = <
44 pinctrl-single,pins = <
[all …]
Dam3517.dtsi4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
14 /delete-node/ &aes1_target;
15 /delete-node/ &aes2_target;
25 /* Based on OMAP3630 variants OPP50 and OPP100 */
26 operating-points-v2 = <&cpu0_opp_table>;
28 clock-latency = <300000>; /* From legacy driver */
32 cpu0_opp_table: opp-table {
33 compatible = "operating-points-v2-ti-cpu";
40 opp50-300000000 {
41 opp-hz = /bits/ 64 <300000000>;
[all …]
Domap3-beagle.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
15 cpu0-supply = <&vcc>;
30 compatible = "gpio-leds";
38 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
39 linux,default-trigger = "heartbeat";
44 gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
45 linux,default-trigger = "mmc0";
[all …]
/Linux-v5.15/arch/arm/mach-omap2/
Dprm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP2+ common Power & Reset Management (PRM) IP block functions
6 * Tero Kristo <t-kristo@ti.com>
10 * underlying registers are located in the PRM on OMAP3/4.
17 #include <linux/init.h>
24 #include <linux/clk-provider.h>
44 * omap_prcm_register_chain_handler() could allocate this based on the
59 * is currently running on. Defined and passed by initialization code
70 * prm_ll_data: function pointers to SoC-specific implementations of
86 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
[all …]
Dwd_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OMAP2+ MPU WD_TIMER-specific code
12 #include <linux/platform_data/omap-wd-timer.h>
23 * settings, WDT module is reset during init. This enables the watchdog
24 * timer. Hence it is required to disable the watchdog after the WDT reset
25 * during init. Otherwise the system would reboot as per the default
37 return -EINVAL; in omap2_wd_timer_disable()
43 oh->name, __func__); in omap2_wd_timer_disable()
44 return -EINVAL; in omap2_wd_timer_disable()
60 * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
[all …]
Domap_hwmod.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
13 * These headers and macros are used to define OMAP on-chip module
16 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * - add interconnect error log structures
21 * - init_conn_id_bit (CONNID_BIT_VECTOR)
22 * - implement default hwmod SMS/SDRC flags?
23 * - move Linux-specific data ("non-ROM data") out
29 #include <linux/init.h>
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/bus/
Dti-sysc.txt20 - compatible shall be one of the following generic types:
23 "ti,sysc-omap2"
24 "ti,sysc-omap4"
25 "ti,sysc-omap4-simple"
30 "ti,sysc-omap2-timer"
31 "ti,sysc-omap4-timer"
32 "ti,sysc-omap3430-sr"
33 "ti,sysc-omap3630-sr"
34 "ti,sysc-omap4-sr"
35 "ti,sysc-omap3-sham"
[all …]
/Linux-v5.15/drivers/clk/
Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
9 #include <linux/init.h>
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_data_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
[all …]
/Linux-v5.15/Documentation/hwmon/
Dw83791d.rst10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
[all …]
/Linux-v5.15/drivers/firewire/
Dinit_ohci1394_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
5 * Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de>
7 * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
9 * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
10 * - reset and initialize them and make them join the IEEE1394 bus and
11 * - enable physical DMA on them to allow remote debugging
18 * be sure that the stack enables it and (re-)attach after the bus reset
28 #include <asm/pci-direct.h> /* for direct PCI config space access */
42 writel(data, ohci->registers + offset); in reg_write()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dcs42l42.txt5 - compatible : "cirrus,cs42l42"
7 - reg : the I2C address of the device for I2C.
9 - VP-supply, VCP-supply, VD_FILT-supply, VL-supply, VA-supply :
15 - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
18 - interrupts : IRQ line info CS42L42.
19 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
22 - cirrus,ts-inv : Boolean property. For jacks that invert the tip sense
27 0 = (Default) Non-inverted
30 - cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no
31 debounce, the tip sense pin might be noisy on a plug event.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/gpio/
Dti,omap-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 The general-purpose interface combines general-purpose input/output (GPIO) banks.
14 Each GPIO banks provides up to 32 dedicated general-purpose pins with input
15 and output capabilities; interrupt generation in active mode and wake-up
21 - enum:
22 - ti,omap2-gpio
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_reset.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
43 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
54 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
59 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
61 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
63 ctx->name, score, in client_mark_guilty()
64 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
75 if (intel_context_is_closed(rq->context)) in mark_guilty()
79 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/omap/
Domap.txt5 On top of that an omap_device is created to extend the platform_device
11 to move data from hwmod to device-tree representation.
15 - compatible: Every devices present in OMAP SoC should be in the
17 - ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
22 - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
24 - ti,no-reset-on-init: When present, the module should not be reset at init
25 - ti,no-idle-on-init: When present, the module should not be idled at init
26 - ti,no-idle: When present, the module is never allowed to idle.
31 compatible = "ti,omap4-spinlock";
37 - General Purpose devices
[all …]
/Linux-v5.15/drivers/net/ethernet/intel/igc/
Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
25 * on the last TLP read/write transaction when MAC is reset. in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
42 hw_dbg("Issuing a global reset to MAC\n"); in igc_reset_hw_base()
49 * where there is no eeprom and prevents getting link. in igc_reset_hw_base()
62 * igc_init_nvm_params_base - Init NVM func ptrs.
67 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_base()
74 /* Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_base()
[all …]
/Linux-v5.15/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
14 If unsure, say no.
19 tristate "Altera Arria10 System Resource Reset"
20 depends on MFD_ALTERA_A10SR
22 This option enables support for the external reset functions for
23 peripheral PHYs on the Altera Arria10 System Resource Chip.
[all …]
/Linux-v5.15/net/dccp/
Dinput.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 /* rate-limit for syncs in reply to sequence-invalid packets; RFC 4340, 7.5.4 */
24 __skb_pull(skb, dccp_hdr(skb)->dccph_doff * 4); in dccp_enqueue_skb()
25 __skb_queue_tail(&sk->sk_receive_queue, skb); in dccp_enqueue_skb()
27 sk->sk_data_ready(sk); in dccp_enqueue_skb()
33 * On receiving Close/CloseReq, both RD/WR shutdown are performed. in dccp_fin()
35 * receiving the closing segment, but there is no guarantee that such in dccp_fin()
38 sk->sk_shutdown = SHUTDOWN_MASK; in dccp_fin()
47 switch (sk->sk_state) { in dccp_rcv_close()
50 * - CLOSED (may be a late or duplicate packet) in dccp_rcv_close()
[all …]
Dipv4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 * The per-net v4_ctl_sk socket is used for responding to
41 * the Out-of-the-blue (OOTB) packets. A control sock will be created
57 dp->dccps_role = DCCP_ROLE_CLIENT; in dccp_v4_connect()
60 return -EINVAL; in dccp_v4_connect()
62 if (usin->sin_family != AF_INET) in dccp_v4_connect()
63 return -EAFNOSUPPORT; in dccp_v4_connect()
65 nexthop = daddr = usin->sin_addr.s_addr; in dccp_v4_connect()
67 inet_opt = rcu_dereference_protected(inet->inet_opt, in dccp_v4_connect()
69 if (inet_opt != NULL && inet_opt->opt.srr) { in dccp_v4_connect()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_fence.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
48 * are no longer in use by the associated ring on the GPU and
67 return -ENOMEM; in amdgpu_fence_slab_init()
84 if (__f->base.ops == &amdgpu_fence_ops) in to_amdgpu_fence()
91 * amdgpu_fence_write - write a fence value
100 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_fence_write()
102 if (drv->cpu_addr) in amdgpu_fence_write()
103 *drv->cpu_addr = cpu_to_le32(seq); in amdgpu_fence_write()
107 * amdgpu_fence_read - read a fence value
116 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_fence_read()
[all …]
/Linux-v5.15/Documentation/PCI/
Dpci-error-recovery.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - Linas Vepstas <linasvepstas@gmail.com>
9 - Richard Lary <rlary@us.ibm.com>
10 - Mike Mason <mmlnx@us.ibm.com>
14 PCI errors on the bus, such as parity errors on the data and address
16 chipsets are able to deal with these errors; these include PCI-E chipsets,
17 and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
22 offered, so that the affected PCI device(s) are reset and put back
23 into working condition. The reset phase requires coordination
32 including multiple instances of a device driver on multi-function
[all …]
/Linux-v5.15/drivers/phy/st/
Dphy-stih407-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/reset.h>
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
65 return reset_control_deassert(phy_dev->rstport); in stih407_usb2_init_port()
73 * Only port reset is asserted, phy global reset is kept untouched in stih407_usb2_exit_port()
74 * as other ports may still be active. When all ports are in reset in stih407_usb2_exit_port()
75 * state, assumption is made that power will be cut off on the phy, in in stih407_usb2_exit_port()
[all …]
/Linux-v5.15/include/linux/platform_data/
Dbrcmfmac.h10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
34 * Note: the brcmfmac can be loaded as module or be statically built-in into
35 * the kernel. If built-in then do note that it uses module_init (and
38 * it built-in to the kernel then use a higher initcall then device_initcall
39 * (see init.h). If this is not done then brcmfmac will load without problems
43 * without reporting anything and just assume there is no data needed. Which is
48 * enum brcmf_bus_type - Bus type identifier. Currently SDIO, USB and PCIE are
59 * struct brcmfmac_sdio_pd - SDIO Device specific platform data.
66 * which will be used depends on the capabilities of the
69 * in-band interrupts are relatively slow and for having
[all …]
/Linux-v5.15/drivers/misc/habanalabs/common/
Ddevice.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
20 if (atomic_read(&hdev->in_reset)) in hl_device_status()
22 else if (hdev->needs_reset) in hl_device_status()
24 else if (hdev->disabled) in hl_device_status()
26 else if (!hdev->init_done) in hl_device_status()
64 hdev = hpriv->hdev; in hpriv_release()
66 put_pid(hpriv->taskpid); in hpriv_release()
70 mutex_destroy(&hpriv->restore_phase_mutex); in hpriv_release()
72 mutex_lock(&hdev->fpriv_list_lock); in hpriv_release()
[all …]
/Linux-v5.15/arch/arm/mach-tegra/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-tegra/reset.c
10 #include <linux/init.h>
19 #include <asm/hardware/cache-l2x0.h>
23 #include "reset.h"
39 * NOTE: This must be the one and only write to the EVP CPU reset in tegra_cpu_reset_handler_set()
47 * Prevent further modifications to the physical reset vector. in tegra_cpu_reset_handler_set()
48 * NOTE: Has no effect on chips prior to Tegra30. in tegra_cpu_reset_handler_set()
71 case -ENOSYS: in tegra_cpu_reset_handler_enable()
78 pr_crit("Cannot set CPU reset handler: %d\n", err); in tegra_cpu_reset_handler_enable()

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