/Linux-v5.10/Documentation/devicetree/bindings/mtd/ |
D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NAND Chip and NAND Controller Generic Binding 10 - Miquel Raynal <miquel.raynal@bootlin.com> 11 - Richard Weinberger <richard@nod.at> 14 The NAND controller should be represented with its own DT node, and 15 all NAND chips attached to this controller should be defined as 16 children nodes of the NAND controller. This representation should be [all …]
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D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller 4 - compatible: Must be one of: 5 - "nvidia,tegra20-nand" 6 - reg: MMIO address range 7 - interrupts: interrupt output of the NFC controller 8 - clocks: Must contain an entry for each entry in clock-names. 9 See ../clocks/clock-bindings.txt for details. 10 - clock-names: Must include the following entries: 11 - nand 12 - resets: Must contain an entry for each entry in reset-names. [all …]
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D | allwinner,sun4i-a10-nand.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A10 NAND Controller Device Tree Bindings 10 - $ref: "nand-controller.yaml" 13 - Chen-Yu Tsai <wens@csie.org> 14 - Maxime Ripard <mripard@kernel.org> 17 "#address-cells": true 18 "#size-cells": true [all …]
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D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller 3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings. 6 - compatible: "oxsemi,ox820-nand" 7 - reg: Base address and length for NAND mapped memory. 10 - clocks: phandle to the NAND gate clock if needed. 11 - resets: phandle to the NAND reset control if needed. 15 nandc: nand-controller@41000000 { 16 compatible = "oxsemi,ox820-nand"; 20 #address-cells = <1>; 21 #size-cells = <0>; [all …]
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D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC) 4 - compatible: can be one of the following: 5 * "marvell,armada-8k-nand-controller" 6 * "marvell,armada370-nand-controller" 7 * "marvell,pxa3xx-nand-controller" 8 * "marvell,armada-8k-nand" (deprecated) 9 * "marvell,armada370-nand" (deprecated) 10 * "marvell,pxa3xx-nand" (deprecated) 13 - reg: NAND flash controller memory area. 14 - #address-cells: shall be set to 1. Encode the NAND CS. [all …]
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D | mxic-nand.txt | 1 Macronix Raw NAND Controller Device Tree Bindings 2 ------------------------------------------------- 5 - compatible: should be "mxic,multi-itfc-v009-nand-controller" 6 - reg: should contain 1 entry for the registers 7 - #address-cells: should be set to 1 8 - #size-cells: should be set to 0 9 - interrupts: interrupt line connected to this raw NAND controller 10 - clock-names: should contain "ps", "send" and "send_dly" 11 - clocks: should contain 3 phandles for the "ps", "send" and 15 - children nodes represent the available NAND chips. [all …]
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/Linux-v5.10/drivers/mtd/nand/raw/ |
D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de> 10 #include <linux/dma-mapping.h> 31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20) 37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4) 38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0) 153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off)) 182 struct mtd_oob_region ecc; member 204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc() 208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc() [all …]
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D | davinci_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips 8 * Sander Huijsen <Shuijsen@optelecom-nkf.com> 24 #include <linux/platform_data/mtd-davinci.h> 25 #include <linux/platform_data/mtd-davinci-aemif.h> 28 * This is a device driver for the NAND flash controller found on the 33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC 34 * available on chips like the DM355 and OMAP-L137 and needed with the 35 * more error-prone MLC NAND chips. 37 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY [all …]
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D | plat_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Generic NAND driver 24 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in plat_nand_attach_chip() 26 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip() 27 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip() 37 * Probe for the NAND device. 41 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe() 49 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe() 50 return -EINVAL; in plat_nand_probe() 53 if (pdata->chip.nr_chips < 1) { in plat_nand_probe() [all …]
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D | socrates_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only 32 * socrates_nand_write_buf - write buffer to chip 33 * @this: NAND chip object 44 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf() 51 * socrates_nand_read_buf - read chip data into buffer 52 * @this: NAND chip object 65 out_be32(host->io_base, val); in socrates_nand_read_buf() 67 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf() 73 * socrates_nand_read_byte - read one byte from the chip 84 * Hardware specific access to control-lines [all …]
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D | pasemi_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2006-2007 PA Semi, Inc 8 * Driver for the PWRficient onchip NAND flash interface 33 static const char driver_name[] = "pasemi-nand"; 38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf() 40 len -= 0x800; in pasemi_read_buf() 42 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); in pasemi_read_buf() 49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf() 51 len -= 0x800; in pasemi_write_buf() 53 memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); in pasemi_write_buf() [all …]
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D | xway_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de> 14 /* nand registers */ 18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */ 19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */ 24 * nand commands 25 * The pins of the NAND chip are selected based on the address bits of the 41 /* we need to tel the ebu which addr we mapped the nand to */ 45 /* we need to tell the EBU that we have nand attached and set it up properly */ 76 return readb(data->nandaddr + op); in xway_readb() [all …]
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D | au1550nd.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #include <asm/mach-au1x00/au1000.h> 15 #include <asm/mach-au1x00/au1550nd.h> 32 * au_write_buf - write buffer to chip 33 * @this: NAND chip object 47 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf() 53 * au_read_buf - read chip data into buffer 54 * @this: NAND chip object 68 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf() 74 * au_write_buf16 - write buffer to chip [all …]
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D | orion_nand.c | 2 * NAND support for Marvell Orion SoC platforms 22 #include <linux/platform_data/mtd-orion_nand.h> 40 offs = (1 << board->cle); in orion_nand_cmd_ctrl() 42 offs = (1 << board->ale); in orion_nand_cmd_ctrl() 46 if (nc->options & NAND_BUSWIDTH_16) in orion_nand_cmd_ctrl() 49 writeb(cmd, nc->legacy.IO_ADDR_W + offs); in orion_nand_cmd_ctrl() 54 void __iomem *io_base = chip->legacy.IO_ADDR_R; in orion_nand_read_buf() 62 len--; in orion_nand_read_buf() 88 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in orion_nand_attach_chip() 90 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in orion_nand_attach_chip() [all …]
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D | gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 * Device driver for NAND flash that uses a memory mapped interface to 11 * read/write the NAND commands and data, and GPIO pins for control signals 12 * (the DT binding refers to this as "GPIO assisted NAND flash") 25 #include <linux/mtd/nand-gpio.h> 52 * Make sure the GPIO state changes occur in-order with writes to NAND 54 * Needed on PXA due to bus-reordering within the SoC itself (see section on 61 if (gpiomtd->io_sync) { in gpio_nand_dosync() 64 * What's required is what's here - a read from a separate in gpio_nand_dosync() 67 tmp = readl(gpiomtd->io_sync); in gpio_nand_dosync() [all …]
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D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Marvell NAND flash controller driver 6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com> 9 * This NAND controller driver handles two versions of the hardware, 13 * The main visible difference is that NFCv1 only has Hamming ECC 14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA 17 * The ECC layouts are depicted in details in Marvell AN-379, but here 21 * or 4) and each chunk will have its own ECC "digest" of 6B at the 28 * +-------------------------------------------------------------+ 29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes | [all …]
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D | nand_base.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * This is the generic MTD driver for NAND flash devices. It should be 5 * capable of working with almost all NAND chips currently available. 8 * http://www.linux-mtd.infradead.org/doc/nand.html 11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 21 * Check, if mtd->ecctype should be set to MTD_ECC_HW 22 * if we have HW ECC support. 37 #include <linux/mtd/nand.h> 52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info() 59 info->group = 0; in nand_pairing_dist3_get_info() [all …]
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D | s3c2410.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright © 2004-2008 Simtec Electronics 7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver 10 #define pr_fmt(fmt) "nand-s3c2410: " fmt 36 #include <linux/platform_data/mtd-nand-s3c2410.h> 73 /* new oob placement block for use with hardware ecc generation 79 return -ERANGE; in s3c2410_ooblayout_ecc() 81 oobregion->offset = 0; in s3c2410_ooblayout_ecc() 82 oobregion->length = 3; in s3c2410_ooblayout_ecc() 91 return -ERANGE; in s3c2410_ooblayout_free() [all …]
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/Linux-v5.10/arch/arm/boot/dts/ |
D | bcm5301x-nand-cs0-bch8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Broadcom BCM470X / BCM5301X Nand chip defaults. 5 * This should be included if the NAND controller is on chip select 0 6 * and uses 8 bit ECC. 8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de> 11 #include "bcm5301x-nand-cs0.dtsi" 14 nand-ecc-algo = "bch"; 15 nand-ecc-strength = <8>; 16 nand-ecc-step-size = <512>;
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D | bcm5301x-nand-cs0-bch1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Broadcom Northstar NAND. 8 #include "bcm5301x-nand-cs0.dtsi" 11 nand-ecc-algo = "bch"; 12 nand-ecc-strength = <1>; 13 nand-ecc-step-size = <512>;
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D | bcm5301x-nand-cs0-bch4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 6 #include "bcm5301x-nand-cs0.dtsi" 9 nand-ecc-algo = "bch"; 10 nand-ecc-strength = <4>; 11 nand-ecc-step-size = <512>;
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D | ox820-cloudengines-pogoplug-series-3.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 8 /dts-v1/; 18 stdout-path = "serial0:115200n8"; 33 compatible = "gpio-leds"; 38 default-state = "keep"; 44 default-state = "keep"; 50 default-state = "keep"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_uart0>; [all …]
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/Linux-v5.10/drivers/mtd/nand/ |
D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Generic Error-Correcting Code (ECC) engine 10 * This file describes the abstraction of any NAND ECC engine. It has been 11 * designed to fit most cases, including parallel NANDs and SPI-NANDs. 13 * There are three main situations where instantiating this ECC engine makes 15 * - external: The ECC engine is outside the NAND pipeline, typically this 16 * is a software ECC engine, or an hardware engine that is 17 * outside the NAND controller pipeline. 18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the 19 * controller's side. This is the case of most of the raw NAND [all …]
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/Linux-v5.10/include/linux/mtd/ |
D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright 2017 - Free Electrons 6 * Boris Brezillon <boris.brezillon@free-electrons.com> 18 * struct nand_memory_organization - Memory organization structure 19 * @bits_per_cell: number of bits per NAND cell 27 * @ntargets: total number of targets exposed by the NAND device 55 * struct nand_row_converter - Information needed to convert an absolute offset 67 * struct nand_pos - NAND position object 68 * @target: the NAND target/die 74 * These information are usually used by specific sub-layers to select the [all …]
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D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 8 * Contains standard defines and IDs for NAND flash devices 17 #include <linux/mtd/nand.h> 21 #include <linux/mtd/nand.h> 29 /* The maximum number of NAND chips in an array */ 50 * Standard NAND flash commands 73 #define NAND_CMD_NONE -1 82 #define NAND_DATA_IFACE_CHECK_ONLY -1 85 * Constants for Hardware ECC [all …]
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