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/Linux-v5.15/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
35 +----------------+-------
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/Linux-v5.15/drivers/memory/
Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
17 #include <dt-bindings/memory/mt2701-larb-port.h>
18 #include <dt-bindings/memory/mtk-memory-port.h>
26 /* mt2701 */
29 /* every register control 8 port, register offset 0x4 */
35 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
36 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
37 * or non-security.
41 /* mt2701 domain should be set to 3 */
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/Linux-v5.15/arch/arm/boot/dts/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/Linux-v5.15/Documentation/devicetree/bindings/media/
Dmediatek-jpeg-decoder.txt6 - compatible : must be one of the following string:
7 "mediatek,mt8173-jpgdec"
8 "mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
9 "mediatek,mt2701-jpgdec"
10 - reg : physical base address of the jpeg decoder registers and length of
12 - interrupts : interrupt number to the interrupt controller.
13 - clocks: device clocks, see
14 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "jpgdec-smi" and "jpgdec".
16 - power-domains: a phandle to the power domain, see
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Dmediatek-jpeg-encoder.txt6 - compatible : "mediatek,mt2701-jpgenc"
7 followed by "mediatek,mtk-jpgenc"
8 - reg : physical base address of the JPEG encoder registers and length of
10 - interrupts : interrupt number to the interrupt controller.
11 - clocks: device clocks, see
12 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
14 - power-domains: a phandle to the power domain, see
16 - mediatek,larb: must contain the local arbiters in the current SoCs, see
17 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
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/Linux-v5.15/include/dt-bindings/memory/
Dmt2701-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
12 * the first port's id for larb[N] would be the last port's id of larb[N - 1]
13 * plus one while larb[0]'s first port number is 0. The definition of
15 * But m4u generation 2 like mt8173 have different port number, it use fixed
16 * offset for each larb, the first port's id for larb[N] would be (N * 32).
23 #define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET) argument
24 #define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET) argument
25 #define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET) argument
27 /* Port define for larb0 */
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/Linux-v5.15/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
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/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
18 generation 1: mt2701 and mt7623.
22 register which control the iommu port is at each larb's register base. But
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
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/Linux-v5.15/drivers/iommu/
Dmtk_iommu_v1.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2016 MediaTek Inc.
15 #include <linux/dma-mapping.h>
30 #include <asm/dma-iommu.h>
32 #include <dt-bindings/memory/mt2701-larb-port.h>
78 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
112 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) in mt2701_m4u_to_larb()
121 int larb = mt2701_m4u_to_larb(id); in mt2701_m4u_to_port() local
123 return id - mt2701_m4u_in_larb[larb]; in mt2701_m4u_to_port()
129 data->base + REG_MMU_INV_SEL); in mtk_iommu_tlb_flush_all()
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