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7 * This is a test that ensures that non-mixed-width vCPUs (all 64bit vCPUs8 * or all 32bit vcPUs) can be configured and mixed-width vCPUs cannot be72 * configured, and two mixed-width vCPUs cannot be configured.110 /* Test with mixed-width vCPUs */ in main()115 "Configuring mixed-width vCPUs worked unexpectedly"); in main()118 "Configuring mixed-width vCPUs worked unexpectedly"); in main()
18 * first data is being mixed to mixout module. When data is not mixed22 * during transition from RUNNING to PAUSED. When data is not mixed24 * When first data is mixed then value "0"is reported.
25 * qspinlock also heavily relies on mixed size atomic operations, in specific30 * Further reading on mixed size atomics that might be relevant:32 * http://www.cl.cam.ac.uk/~pes20/popl17/mixed-size.pdf
65 Note: All the cpus on the system must have mixed endian support at EL066 for this feature to be enabled. If a new CPU - which doesn't support mixed
38 #define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */39 #define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
43 into 21h (headphone jack on my machine). Mixed signal respects the mute48 into 14h (internal speaker on my machine). Mixed signal **ignores** the mute102 then amplified and mixed into both the headphones and the speakers. Not only
39 - mode 2 : single ended and differential mixed61 - 2 = single ended and differential mixed
1 # mixed key and subkeys with braces
3 # mixed key value can be overridden
74 * - Mixed-endian76 * - Mixed-endian at EL0 only
41 # It is forbidden in mlxsw driver to have mixed-bound66 check_fail $? "Incorrect success to add drop rule to mixed bound block"116 check_fail $? "Incorrect success to add redirect rule to mixed bound block"
3 # -Wno-declaration-after-statement: The python headers have mixed code with declarations (decls aft…
9 * This is useful for systems with mixed controllable and
29 * ARMv6+ -mbig-endian generates mixed endianness code vs data: little-endian50 * data endianness will be mixed before the linker is invoked. So rather
5 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
21 I3C bus mode. Can be "pure", "mixed-fast" or "mixed-slow". See
13 The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
8 # -Wno-declaration-after-statement: The python headers have mixed code with declarations (decls aft…
3 * thunks_32.S - assembly helpers for mixed-bitness code
3 * thunks.S - assembly helpers for mixed-bitness code
725 * blk_rq_set_mixed_merge - mark a request as mixed merge726 * @rq: request to mark as mixed merge729 * @rq is about to be mixed merged. Make sure the attributes730 * which can be mixed are set in each bio and mark @rq as mixed843 * a mixed merge, mark both as mixed before proceeding. This in attempt_merge()
345 __description("PTR_TO_STACK mixed reg/k, 1")362 __description("PTR_TO_STACK mixed reg/k, 2")384 __description("PTR_TO_STACK mixed reg/k, 3")
177 let mixed-accesses = ([Plain & W] ; (po-loc \ barrier) ; [Marked]) |179 flag ~empty mixed-accesses as mixed-accesses
296 u8 mixed; member360 u8 mixed; member
5 partitions or non standard bootloader partition sizes. For these a mixed layout
