| /Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power10/ |
| D | memory.json | 10 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
15 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
25 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
30 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
35 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
40 …ing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructi…
60 … MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand…
70 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
75 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
80 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes Chg2X)",
117 "BriefDescription": "L1 ITLB Misses",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes Chg2X)",
117 "BriefDescription": "L1 ITLB Misses",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes cacheline state change requests)",
153 "BriefDescription": "L1 ITLB Misses",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
13 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
18 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
58 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
77 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
87 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
97 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
[all …]
|
| D | hsw-metrics.json | 7 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
15 …ed due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch st…
19 …: "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
30 …nts fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB…
118 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
142 …the first-level data TLB (assuming worst case scenario with back to back misses to different pages…
154 … "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operat…
158 … "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operat…
182 …. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
13 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
18 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
58 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
77 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
87 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
97 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
57 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
68 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
79 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
95 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
57 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
68 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
79 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
95 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
57 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
68 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
79 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
95 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| D | virtual-memory.json | 14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
60 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
95 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
106 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any pag…
117 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
129 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
141 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | virtual-memory.json | 14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
60 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
95 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
106 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any pag…
117 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
129 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
141 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | virtual-memory.json | 17 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
37 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
52 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
72 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
111 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
116 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
121 "BriefDescription": "Misses at all ITLB levels that cause page walks",
126 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
141 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
146 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
|
| D | ivb-metrics.json | 7 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
15 …ed due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch st…
19 …: "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
30 …nts fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB…
118 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
142 …the first-level data TLB (assuming worst case scenario with back to back misses to different pages…
154 … "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operat…
158 … "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operat…
182 …. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/bonnell/ |
| D | virtual-memory.json | 11 "BriefDescription": "DTLB misses due to load operations.",
19 "BriefDescription": "DTLB misses due to store operations.",
27 "BriefDescription": "L0 DTLB misses due to load operations.",
35 "BriefDescription": "L0 DTLB misses due to store operations",
59 "BriefDescription": "ITLB misses.",
62 "EventName": "ITLB.MISSES",
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
22 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
36 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
41 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
59 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
95 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
113 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
127 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
22 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
36 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
41 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
59 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
95 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
113 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
127 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | virtual-memory.json | 35 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
55 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
70 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
90 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
129 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
134 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
139 "BriefDescription": "Misses at all ITLB levels that cause page walks",
144 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
159 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
164 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
|
| /Linux-v6.1/tools/perf/tests/shell/ |
| D | stat.sh | 78 …structions,branch-misses,bus-cycles,cache-misses,cache-references,cpu-cycles,instructions,mem-load…
84 …structions,branch-misses,bus-cycles,cache-misses,cache-references,cpu-cycles,instructions,mem-load…
|
| /Linux-v6.1/tools/perf/pmu-events/arch/test/test_soc/cpu/ |
| D | uncore.json | 14 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c…
15 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor …
47 "BriefDescription": "Total cache misses",
48 "PublicDescription": "Total cache misses",
|
| /Linux-v6.1/arch/arm/kernel/ |
| D | perf_event_v6.c | 74 * accesses/misses in hardware.
93 * accesses/misses so this isn't strictly correct, but it's the best we
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
142 * accesses/misses in hardware.
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
168 * misses and main TLB misses. There isn't an event for TLB misses, so
169 * use the micro misses here and if users want the main TLB misses they
|
| /Linux-v6.1/arch/powerpc/perf/ |
| D | power8-pmu.c | 128 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
130 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
142 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
145 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
148 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
150 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
151 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
|
| D | generic-compat-pmu.c | 106 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
107 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
111 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
112 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
113 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
114 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
115 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
|
| D | power10-pmu.c | 124 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
126 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
130 GENERIC_EVENT_ATTR(branch-misses, PM_MPRED_BR_FIN);
131 GENERIC_EVENT_ATTR(cache-misses, PM_LD_DEMAND_MISS_L1_FIN);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
140 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
143 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
145 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
[all …]
|
| D | power9-pmu.c | 171 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
173 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
184 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
187 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
189 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
190 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
|
