| /Linux-v5.4/tools/perf/pmu-events/arch/x86/haswell/ |
| D | virtual-memory.json | 3 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
9 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
13 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
23 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
42 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
52 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
68 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
78 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
92 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
98 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
[all …]
|
| D | hsw-metrics.json | 4 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
11 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
32 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
39 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
83 … ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
192 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
198 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
222 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
228 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
234 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
[all …]
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | virtual-memory.json | 5 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
18 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
28 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
47 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
57 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
64 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
74 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
94 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
97 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
[all …]
|
| D | uncore-cache.json | 10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
75 … "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
86 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
97 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
|
| D | hsx-metrics.json | 4 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
11 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
32 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
39 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
83 … ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
192 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
198 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
222 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
228 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
234 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
[all …]
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 3 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
10 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
14 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
25 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
36 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
73 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
82 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
95 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
102 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
106 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
[all …]
|
| D | bdw-metrics.json | 4 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
11 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
32 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
39 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
83 … ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
216 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
222 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
246 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
252 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
258 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
[all …]
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 5 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
20 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
31 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
42 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
70 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
79 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
97 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
112 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
[all …]
|
| D | uncore-cache.json | 10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
75 … "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
86 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
97 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 5 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
20 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
31 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
42 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
70 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
79 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
97 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
112 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
[all …]
|
| D | uncore-cache.json | 10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
75 … "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
86 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
97 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | uncore-cache.json | 10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.un…
53 …"BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_p…
64 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
75 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
86 …"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_in…
97 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.…
108 …"BriefDescription": "LLC misses for ItoM writes (as part of fast string memcpy stores). Derived fr…
119 …"BriefDescription": "LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opco…
[all …]
|
| D | virtual-memory.json | 3 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
22 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
66 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
76 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
119 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
125 "BriefDescription": "Misses at all ITLB levels that cause page walks",
129 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
135 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
159 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
165 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
|
| D | ivt-metrics.json | 4 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
11 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
32 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
39 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
83 … / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )",
204 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
210 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
234 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
240 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
246 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
[all …]
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/tremontx/ |
| D | uncore-other.json | 11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
183 "BriefDescription": "TOR Inserts; CRd misses from local IA",
189 "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter",
195 "BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
201 …"PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filte…
207 "BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
213 … "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
219 "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
225 …"PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop f…
231 "BriefDescription": "TOR Inserts; RFO misses from local IA",
[all …]
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | virtual-memory.json | 3 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
13 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
48 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
58 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
101 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
107 "BriefDescription": "Misses at all ITLB levels that cause page walks",
111 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
117 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
141 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
147 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
|
| D | ivb-metrics.json | 4 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
11 …d could have accepted them. For example; stalls due to instruction-cache misses would be categoriz…
32 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
39 …etired according to program order. For example; stalls due to data-cache misses or stalls due to t…
83 … / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )",
204 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
210 …"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by ins…
234 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
240 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
246 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
[all …]
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/bonnell/ |
| D | virtual-memory.json | 16 "BriefDescription": "DTLB misses due to load operations."
24 "BriefDescription": "L0 DTLB misses due to load operations."
32 "BriefDescription": "DTLB misses due to store operations."
40 "BriefDescription": "L0 DTLB misses due to store operations"
111 "EventName": "ITLB.MISSES",
113 "BriefDescription": "ITLB misses."
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | virtual-memory.json | 26 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
35 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
39 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
63 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
72 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
76 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
101 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
110 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
| D | uncore-cache.json | 10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.un…
53 …"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_in…
64 …"BriefDescription": "LLC misses for ItoM writes (as part of fast string memcpy stores). Derived fr…
174 …"BriefDescription": "Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to g…
|
| /Linux-v5.4/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | virtual-memory.json | 8 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
17 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
21 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
46 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
55 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
91 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
100 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
104 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
|
| /Linux-v5.4/drivers/cpuidle/governors/ |
| D | teo.c | 71 * @misses: CPU wakeups "missing" this state.
91 unsigned int misses; member
166 * Update the "hits" and "misses" data for the state matching the sleep in teo_update()
169 * miss, so increase the "misses" metric for it. In the latter case in teo_update()
175 unsigned int misses = cpu_data->states[idx_timer].misses; in teo_update() local
178 misses -= misses >> DECAY_SHIFT; in teo_update()
181 misses += PULSE; in teo_update()
188 cpu_data->states[idx_timer].misses = misses; in teo_update()
297 * greater than its "misses" metric, that is the one to use. Otherwise, in teo_select()
303 if (cpu_data->states[idx].hits <= cpu_data->states[idx].misses && in teo_select()
|
| /Linux-v5.4/arch/arm/kernel/ |
| D | perf_event_v6.c | 74 * accesses/misses in hardware.
93 * accesses/misses so this isn't strictly correct, but it's the best we
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
142 * accesses/misses in hardware.
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
168 * misses and main TLB misses. There isn't an event for TLB misses, so
169 * use the micro misses here and if users want the main TLB misses they
|
| /Linux-v5.4/arch/powerpc/perf/ |
| D | power8-pmu.c | 128 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
130 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
142 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
145 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
148 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
150 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
151 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
|
| D | power9-pmu.c | 157 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
159 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
163 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
166 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
167 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
170 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
173 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
175 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
176 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
|
