micro\-TLB (full) in projects: Linux-v6.1

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Searched +full:micro +full:- +full:tlb (Results 1 – 25 of 112) sorted by relevance

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/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
D	ifu.json	3 "PublicDescription": "I-Cache miss on an access from the prefetch block", 6 "BriefDescription": "I-Cache miss on an access from the prefetch block" 9 …"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l… 12 …"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l … 15 …"PublicDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 p… 18 …"BriefDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 pr… 21 … "PublicDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor", 24 "BriefDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor" 27 "PublicDescription": "Micro-predictor hit with immediate redirect", 30 "BriefDescription": "Micro-predictor hit with immediate redirect" [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
D	cache.json	111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM", 114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM" 117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM", 120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM" 129 "PublicDescription": "Level 1 PLD TLB refill", 132 "BriefDescription": "Level 1 PLD TLB refill" 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa… 138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar… 141 "PublicDescription": "Level 1 TLB flush", 144 "BriefDescription": "Level 1 TLB flush" [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
D	pipeline.json	10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre… 20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p… 25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" 30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc… 40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/
D	common-and-microarch.json	15 "PublicDescription": "Attributable Level 1 instruction TLB refill", 18 "BriefDescription": "Attributable Level 1 instruction TLB refill" 33 "PublicDescription": "Attributable Level 1 data TLB refill", 36 "BriefDescription": "Attributable Level 1 data TLB refill" 129 "PublicDescription": "Attributable Level 1 data cache write-back", 132 "BriefDescription": "Attributable Level 1 data cache write-back" 147 "PublicDescription": "Attributable Level 2 data cache write-back", 150 "BriefDescription": "Attributable Level 2 data cache write-back" 219 "PublicDescription": "Attributable Level 1 data or unified TLB access", 222 "BriefDescription": "Attributable Level 1 data or unified TLB access" [all …]
/Linux-v6.1/arch/powerpc/platforms/8xx/
D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)" 39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE. 42 bool "Analogue & Micro Adder 875" 45 This enables support for the Analogue & Micro Adder 875 56 menu "Freescale Ethernet driver platform-specific options" 76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2 77 (often 2-nd UART) will not work if this is enabled. 83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1 84 (often 1-nd UART) will not work if this is enabled. [all …]
/Linux-v6.1/arch/arm/kernel/
D	perf_event_v6.c	1 // SPDX-License-Identifier: GPL-2.0 17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This 19 * - disable the counter's interrupt generation (each counter has it's 24 * - enable the counter's interrupt generation. 25 * - set the new event type. 30 * ignoring that counter. When re-enabling, we have to reset the value and 104 * The ARM performance counters can count micro DTLB misses, micro ITLB 105 * misses and main TLB misses. There isn't an event for TLB misses, so 106 * use the micro misses here and if users want the main TLB misses they 167 * The ARM performance counters can count micro DTLB misses, micro ITLB [all …]
/Linux-v6.1/tools/perf/Documentation/
D	perf-arm-spe.txt	`1 perf-arm-spe(1) 5 ---- 6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools 9 -------- 11 'perf record' -e arm_spe// 14 ----------- 17 events down to individual instructions. Rather than being interrupt-driven, it picks an 33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The 35 sample. This minimum interval is used by the driver if no interval is specified. A pseudo-random 62 ---------------- [all …]`
/Linux-v6.1/Documentation/devicetree/bindings/iommu/
D	renesas,ipmmu-vmsa.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas VMSA-Compatible IOMMU 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 connected to the IPMMU through a port called micro-TLB. 20 - items: 21 - enum: 22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6 [all …]`
D	msm,iommu-v0.txt	5 of the CPU, each connected to the IOMMU through a port called micro-TLB. 9 - compatible: Must contain "qcom,apq8064-iommu". 10 - reg: Base address and size of the IOMMU registers. 11 - interrupts: Specifiers for the MMU fault interrupts. For instances that 12 support secure mode two interrupts must be specified, for non-secure and 15 - #iommu-cells: The number of cells needed to specify the stream id. This 17 - qcom,ncb: The total number of context banks in the IOMMU. 18 - clocks : List of clocks to be used during SMMU register access. See 19 Documentation/devicetree/bindings/clock/clock-bindings.txt 21 here, there must be a corresponding entry in clock-names [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/
D	snb-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 19 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 23 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 31 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 39 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 55 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 60 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 68 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /… 71 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/
D	jkt-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 19 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 23 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 31 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 39 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 55 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 60 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 68 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /… 71 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… [all …]
/Linux-v6.1/arch/mips/mm/
D	tlb-funcs.S	`6 * Micro-assembler generated tlb handler functions. 10 * Based on mm/page-funcs.c 12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>`
/Linux-v6.1/drivers/edac/
D	mce_amd.c	1 // SPDX-License-Identifier: GPL-2.0-only 71 "PFB non-cacheable bit parity error", 101 "Link-defined sync error packets detected on HT link", 151 "Level 1 TLB parity error", 164 "Level 2 TLB parity error", 174 "An ECC error was detected on a data cache read-modify-write by a store", 179 "An ECC error was detected on an EMEM read-modify-write by a store", 180 "A parity error was detected in an L1 TLB entry by any access", 181 "A parity error was detected in an L2 TLB entry by any access", 200 "IC Microtag or Full Tag Multi-hit Error", [all …]
/Linux-v6.1/arch/arc/mm/
D	tlbex.S	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 TLB Exception Handling for ARC 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 8 * -MMU v1: moved out legacy code into a seperate file 9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB 14 * entry, so that it doesn't knock out it's I-TLB entry 15 * -Some more fine tuning: 19 * -Practically rewrote the I/D TLB Miss handlers 26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen1/
D	recommended.json	`4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 119 "MetricGroup": "tlb" 148 "BriefDescription": "Micro-ops Dispatched", 160 "BriefDescription": "Micro-ops Retired" 168 "ScaleUnit": "3e-5MiB" 172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)", 176 "ScaleUnit": "6.1e-5MiB"`
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen2/
D	recommended.json	`4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 119 "MetricGroup": "tlb" 148 "BriefDescription": "Micro-ops Dispatched", 160 "BriefDescription": "Micro-ops Retired" 168 "ScaleUnit": "3e-5MiB" 172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)", 176 "ScaleUnit": "6.1e-5MiB"`
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/
D	ivb-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses", 26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 30 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/
D	bdx-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 30 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 57 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", 68 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 84 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 89 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 97 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/
D	hsx-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 30 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", 78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or … [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/
D	icx-metrics.json	4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret… 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 27 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 31 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/
D	clx-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 27 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 31 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/
D	skx-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 27 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 31 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivytown/
D	ivt-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses", 26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 30 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/
D	hsw-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 26 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 30 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", 78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or … [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/
D	skl-metrics.json	7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 27 …his metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 31 …etric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Samp… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …SB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delive… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]

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