| /Linux-v6.1/include/linux/ |
| D | resctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
18 /* max value for struct rdt_domain's mbps_val */
22 * enum resctrl_conf_type - The type of configuration.
46 * struct resctrl_staged_config - parsed configuration to be applied
56 * struct rdt_domain - group of CPUs sharing a resctrl resource
61 * @mbm_total: saved state for MBM total bandwidth
62 * @mbm_local: saved state for MBM local bandwidth
67 * @plr: pseudo-locked region (if any) associated with domain
90 * struct resctrl_cache - Cache allocation related data
110 * enum membw_throttle_mode - System's memory bandwidth throttling mode
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/display/ti/ |
| D | ti,k2g-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The K2G DSS is an ultra-light version of TI Keystone Display
21 const: ti,k2g-dss
25 - description: cfg DSS top level
26 - description: common DISPC common
[all …]
|
| D | ti,omap2-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap2-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
16 - Video port for DPI output
19 - data-lines: number of lines used
23 -----
26 - compatible: "ti,omap2-dispc"
27 - reg: address and length of the register space
[all …]
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| D | ti,dra7-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
16 - syscon: phandle to control module core syscon node
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
25 - clocks: handle to video1 pll clock and video2 pll clock
[all …]
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| D | ti,omap3-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
[all …]
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| D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]
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| D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
[all …]
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| D | ti,am65x-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,am65x-dss
26 Addresses to each DSS memory region described in the SoC's TRM.
28 - description: common DSS register area
29 - description: VIDL1 light video plane
[all …]
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| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_bw.c | 1 // SPDX-License-Identifier: MIT
47 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); in dg1_mchbar_read_qgv_point_info()
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
55 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in dg1_mchbar_read_qgv_point_info()
57 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
59 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
60 return -EINVAL; in dg1_mchbar_read_qgv_point_info()
62 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); in dg1_mchbar_read_qgv_point_info()
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/dma/ |
| D | qcom_hidma_mgmt.txt | 8 share the same bandwidth. The bandwidth utilization can be partitioned
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
24 writing into destination memory. Setting this value incorrectly can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
29 reading the source memory. Setting this value incorrectly can starve
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | icx-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/display/ |
| D | arm,pl11x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
15 a framebuffer region in system memory, and creates timed signals for
24 - arm,pl110
25 - arm,pl111
27 - compatible
32 - enum:
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | spr-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
[all …]
|
| /Linux-v6.1/Documentation/x86/ |
| D | resctrl.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
31 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps]] /sys/fs/resctrl
41 bandwidth in MBps
47 pseudo-locking is a unique way of using cache control to "pin" or
49 "Cache Pseudo-Locking".
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | clx-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
95 …bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for ca…
100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | tgl-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | icl-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
[all …]
|
| /Linux-v6.1/drivers/usb/core/ |
| D | urb.c | 1 // SPDX-License-Identifier: GPL-2.0
24 if (urb->transfer_flags & URB_FREE_BUFFER) in urb_destroy()
25 kfree(urb->transfer_buffer); in urb_destroy()
31 * usb_init_urb - initializes a urb so that it can be used by a USB driver
39 * careful when freeing the memory for your urb that it is no longer in
48 kref_init(&urb->kref); in usb_init_urb()
49 INIT_LIST_HEAD(&urb->urb_list); in usb_init_urb()
50 INIT_LIST_HEAD(&urb->anchor_list); in usb_init_urb()
56 * usb_alloc_urb - creates a new urb for a USB driver to use
58 * @mem_flags: the type of memory to allocate, see kmalloc() for a list of
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | skx-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
95 …bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for ca…
100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | adl-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
13 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
16 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
43 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
58 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
79 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
97 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
102 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
103 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | skl-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
95 …bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for ca…
100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
|
| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | intel_llc.c | 1 // SPDX-License-Identifier: MIT
37 max_khz = policy->cpuinfo.max_freq; in cpu_max_MHz()
53 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; in get_ia_constants()
54 struct intel_rps *rps = &llc_to_gt(llc)->rps; in get_ia_constants()
59 consts->max_ia_freq = cpu_max_MHz(); in get_ia_constants()
61 consts->min_ring_freq = in get_ia_constants()
62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; in get_ia_constants()
63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ in get_ia_constants()
64 consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); in get_ia_constants()
66 consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps); in get_ia_constants()
[all …]
|
| /Linux-v6.1/drivers/net/ipa/ |
| D | ipa_data.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2022 Linaro Ltd.
18 * Boot-time configuration data is used to define the configuration of the
22 * channels, memory, power and so on are allocated and used for the
41 * together, establishing the endpoint_id->(EE, channel_id) mapping.
52 /** enum ipa_qsb_master_id - array index for IPA QSB configuration data */
59 * struct ipa_qsb_data - Qualcomm System Bus configuration data
62 * @max_reads_beats: Max outstanding read bytes in 8-byte "beats" (if non-zero)
71 * struct gsi_channel_data - GSI channel configuration data
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | ivb-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses",
38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
46 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
66 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
70 …bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for ca…
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | hsw-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
46 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
66 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
70 …bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for ca…
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …re-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long i…
[all …]
|
