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/Linux-v6.6/Documentation/devicetree/bindings/iommu/
Diommu.txt49 association of masters to be configured. Note that an IOMMU can by design
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
70 Devices that access memory through an IOMMU are called masters. A device can
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
105 Firmware has to opt-in stalling, because most buses and masters don't
108 won't work in systems and masters that haven't been designed for
146 * Masters are statically associated with this IOMMU and share
148 * have sufficient information to distinguish between masters.
151 * all masters at any given point in time.
/Linux-v6.6/Documentation/trace/
Dstm.rst11 these masters and channels are statically allocated to certain
23 master 7 channel 15, while arbitrary user applications can use masters
28 identifiers to ranges of masters and channels. If these rules (policy)
33 have a name (string identifier) and a range of masters and channels
41 channels masters
42 $ cat /config/stp-policy/dummy_stm.my-policy/user/masters
48 masters 48 through 63 and channel allocation pool has channels 0
Dintel_th.rst37 GTH allows directing different STP masters into different output ports
38 via its "masters" attribute group. More detailed GTH interface
79 $ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
/Linux-v6.6/drivers/staging/vme_user/
Dvme_fake.c65 struct fake_master_window masters[FAKE_MAX_MASTER]; member
317 bridge->masters[i].enabled = enabled; in fake_master_set()
318 bridge->masters[i].vme_base = vme_base; in fake_master_set()
319 bridge->masters[i].size = size; in fake_master_set()
320 bridge->masters[i].aspace = aspace; in fake_master_set()
321 bridge->masters[i].cycle = cycle; in fake_master_set()
322 bridge->masters[i].dwidth = dwidth; in fake_master_set()
348 *enabled = bridge->masters[i].enabled; in __fake_master_get()
349 *vme_base = bridge->masters[i].vme_base; in __fake_master_get()
350 *size = bridge->masters[i].size; in __fake_master_get()
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/dma/
Ddma-router.yaml25 dma-masters:
39 - dma-masters
51 dma-masters = <&sdma>;
Dsnps,dw-axi-dmac.yaml65 snps,dma-masters:
67 Number of AXI masters supported by the hardware.
109 - snps,dma-masters
149 snps,dma-masters = <2>;
Drenesas,rzn1-dmamux.yaml30 dma-masters:
49 dma-masters = <&dma0 &dma1>;
Dst,stm32-dmamux.yaml34 - dma-masters
49 dma-masters = <&dma1>, <&dma2>;
Dlpc1850-dmamux.txt12 - dma-masters: phandle pointing to the DMA controller
41 dma-masters = <&dmac>;
Dsnps,dma-spear1340.yaml62 dma-masters:
65 Number of DMA masters supported by the controller. In case if
175 dma-masters = <4>;
Dti-dma-crossbar.txt10 - dma-masters: phandle pointing to the DMA controller
55 dma-masters = <&sdma>;
/Linux-v6.6/drivers/fsi/
Dfsi-master.h4 * to allow the core to interact with the (hardware-specific) masters.
18 * These are used by hardware masters, such as the one in the FSP2, AST2600 and
59 #define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */
77 * These are used by low level masters that bit-bang out the protocol
118 * These are common to all masters
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/
Dmetrics.json3 "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
11 "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/freescale/imx8mn/sys/
Dmetrics.json3 "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
11 "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/
Dmetrics.json3 "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
11 "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
/Linux-v6.6/Documentation/devicetree/bindings/fsi/
Dfsi.txt11 FSI masters may require their own DT nodes (to describe the master HW itself);
15 Under the masters' nodes, we can describe the bus topology using nodes to
43 FSI masters
62 masters that may be present on the bus.
/Linux-v6.6/Documentation/ABI/testing/
Dsysfs-class-stm1 What: /sys/class/stm/<stm>/masters
24 assigned masters.
Dconfigfs-stp-policy34 What: /config/stp-policy/<device>.<policy>/<node>/masters
38 Range of masters from which to allocate for users of this node.
Dsysfs-bus-intel_th-devices-gth1 What: /sys/bus/intel_th/devices/<intel_th_id>-gth/masters/*
5 Description: (RW) Configure output ports for STP masters. Writing -1
/Linux-v6.6/Documentation/devicetree/bindings/arm/
Dcci-control-port.yaml7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
/Linux-v6.6/drivers/soundwire/
Dintel_bus_common.c77 * case if one or more masters remain active. In this condition, in intel_start_bus_after_reset()
78 * all the masters are powered on for they are in the same power in intel_start_bus_after_reset()
254 * all the Masters in the steam with the expectation that in intel_post_bank_switch()
256 * and do nothing for the other Masters in intel_post_bank_switch()
/Linux-v6.6/drivers/i2c/muxes/
Di2c-mux-pca9541.c29 * The PCA9541 is a bus master selector. It supports two I2C masters connected
38 * This driver assumes that the two bus masters are controlled by two different
39 * hosts. If a single host controls both masters, platform code has to ensure
40 * that only one of the masters is instantiated at any given time.
158 * The main contention point occurs if the slave bus is off and both masters
/Linux-v6.6/drivers/dma/
Dstm32-dmamux.c48 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
49 * [0] holds number of DMA Masters.
133 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1); in stm32_dmamux_route_allocate()
192 count = device_property_count_u32(&pdev->dev, "dma-masters"); in stm32_dmamux_probe()
205 dma_node = of_parse_phandle(node, "dma-masters", i - 1); in stm32_dmamux_probe()
/Linux-v6.6/Documentation/devicetree/bindings/bus/
Dbrcm,gisb-arb.yaml40 32-bits wide bitmask used to specify which GISB masters are valid at the
46 String list of the literal name of the GISB masters. Should match the
/Linux-v6.6/Documentation/networking/dsa/
Dconfiguration.rst383 This can be achieved by placing the DSA masters under a LAG interface (bonding
385 on the CPU ports facing the physical DSA masters that constitute the LAG slave
389 the switch must mark all the links between CPU ports and their DSA masters
393 configure the system for the switch to use other masters.
447 static user to CPU port assignment with LAG between DSA masters. It is not
455 Physical DSA masters are allowed to join and leave at any time a LAG interface

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