Searched +full:ls1028a +full:- +full:plldig (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding10 - Wen He <wen.he_1@nxp.com>13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output19 const: fsl,ls1028a-plldig27 '#clock-cells':30 fsl,vco-hz:[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Clock driver for LS1028A Display output interfaces(LCD, DPHY).8 #include <linux/clk-provider.h>21 /* PLLDIG register offsets and bit masks */72 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()78 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()88 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()93 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()100 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()110 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1028A family SoC.5 * Copyright 2018-2020 NXP11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/thermal/thermal.h>16 compatible = "fsl,ls1028a";17 interrupt-parent = <&gic>;18 #address-cells = <2>;19 #size-cells = <2>;[all …]
