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/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dfsl,spi-fsl-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
13 - $ref: "spi-controller.yaml#"
18 - enum:
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
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/Linux-v5.15/arch/arm/boot/dts/
Dls1021a.dtsi2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/thermal/thermal.h>
52 #address-cells = <2>;
53 #size-cells = <2>;
54 compatible = "fsl,ls1021a";
55 interrupt-parent = <&gic>;
73 #address-cells = <1>;
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Dls1021a-twr.dts2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
5 * This file is dual-licensed: you can use it either under the terms
23 * MA 02110-1301 USA
49 /dts-v1/;
50 #include "ls1021a.dtsi"
53 model = "LS1021A TWR Board";
54 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
62 sys_mclk: clock-mclk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
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Dls1021a-moxa-uc-8410a.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include "ls1021a.dtsi"
17 model = "Moxa UC-8410A";
18 compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a";
26 sys_mclk: clock-mclk {
27 compatible = "fixed-clock";
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Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
7 #include "ls1021a.dtsi"
10 model = "NXP LS1021A-TSN Board";
12 sys_mclk: clock-mclk {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <24576000>;
18 reg_vdda_codec: regulator-3V3 {
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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
35 #address-cells = <1>;
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Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
36 #address-cells = <1>;
37 #size-cells = <0>;
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Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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/Linux-v5.15/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
127 supports spi-mem interface.
197 this code to manage the per-word or per-transfer accesses to the
226 Cadence QSPI is a specialized controller for connecting an SPI
227 Flash over 1/2/4-bit wide bus. Enable this option if you have a
228 device with a Cadence QSPI controller and want to access the
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Dspi-fsl-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 * Based on the original fsl-quadspi.c SPI NOR driver:
43 #include <linux/spi/spi-mem.h>
159 #define LUT_PAD(x) (fls(x) - 1)
165 * ---------------------------------------------------
167 * ---------------------------------------------------
280 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; in needs_swap_endian()
285 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; in needs_4x_clock()
290 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; in needs_fill_txfifo()
295 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; in needs_wakeup_wait_mode()
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/Linux-v5.15/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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