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/Linux-v6.6/drivers/gpu/drm/amd/include/ivsrcid/dcn/
Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
/Linux-v6.6/fs/nilfs2/
Dbtree.c26 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_alloc_path() local
32 for (; level < NILFS_BTREE_LEVEL_MAX; level++) { in nilfs_btree_alloc_path()
33 path[level].bp_bh = NULL; in nilfs_btree_alloc_path()
34 path[level].bp_sib_bh = NULL; in nilfs_btree_alloc_path()
35 path[level].bp_index = 0; in nilfs_btree_alloc_path()
36 path[level].bp_oldreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
37 path[level].bp_newreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
38 path[level].bp_op = NULL; in nilfs_btree_alloc_path()
47 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_free_path() local
49 for (; level < NILFS_BTREE_LEVEL_MAX; level++) in nilfs_btree_free_path()
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/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_z16/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This…
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
49 …ress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss i…
56 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
63 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
[all …]
/Linux-v6.6/lib/zstd/compress/
Dclevels.h27 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
28 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
29 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
30 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
31 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
32 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6 */
33 { 21, 19, 20, 4, 5, 8, ZSTD_lazy }, /* level 7 */
34 { 21, 19, 20, 4, 5, 16, ZSTD_lazy2 }, /* level 8 */
35 { 22, 20, 21, 4, 5, 16, ZSTD_lazy2 }, /* level 9 */
36 { 22, 21, 22, 5, 5, 16, ZSTD_lazy2 }, /* level 10 */
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/Linux-v6.6/fs/xfs/scrub/
Dbtree.c29 int level, in __xchk_btree_process_error() argument
51 trace_xchk_ifork_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
54 trace_xchk_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
65 int level, in xchk_btree_process_error() argument
68 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_process_error()
76 int level, in xchk_btree_xref_process_error() argument
79 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_xref_process_error()
88 int level, in __xchk_btree_set_corrupt() argument
95 trace_xchk_ifork_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
98 trace_xchk_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
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Ddabtree.c32 int level, in xchk_da_process_error() argument
55 ds->state->path.blk[level].blkno), in xchk_da_process_error()
69 int level) in xchk_da_set_corrupt() argument
77 ds->state->path.blk[level].blkno), in xchk_da_set_corrupt()
84 int level) in xchk_da_btree_node_entry() argument
86 struct xfs_da_state_blk *blk = &ds->state->path.blk[level]; in xchk_da_btree_node_entry()
99 int level, in xchk_da_btree_hash() argument
108 if (hash < ds->hashes[level]) in xchk_da_btree_hash()
109 xchk_da_set_corrupt(ds, level); in xchk_da_btree_hash()
110 ds->hashes[level] = hash; in xchk_da_btree_hash()
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/Linux-v6.6/arch/s390/include/asm/
Ddebug.h19 #define DEBUG_OFF_LEVEL -1 /* level where debug is switched off */
23 #define DEBUG_DEFAULT_LEVEL 3 /* initial debug level */
35 unsigned long level : 3; member
49 int level; member
100 debug_entry_t *debug_event_common(debug_info_t *id, int level,
103 debug_entry_t *debug_exception_common(debug_info_t *id, int level,
125 * level would be logged. Otherwise returns false.
128 * @level: debug level
131 * - %true if level is less or equal to the current debug level.
133 static inline bool debug_level_enabled(debug_info_t *id, int level) in debug_level_enabled() argument
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/Linux-v6.6/security/selinux/ss/
Dcontext.h45 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy()
46 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy()
50 dst->range.level[1].sens = src->range.level[1].sens; in mls_context_cpy()
51 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[1].cat); in mls_context_cpy()
53 ebitmap_destroy(&dst->range.level[0].cat); in mls_context_cpy()
59 * Sets both levels in the MLS range of 'dst' to the low level of 'src'.
65 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy_low()
66 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy_low()
70 dst->range.level[1].sens = src->range.level[0].sens; in mls_context_cpy_low()
71 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[0].cat); in mls_context_cpy_low()
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/Linux-v6.6/arch/arm/
DKconfig.debug115 bool "Kernel low-level debugging functions (read help!)"
128 prompt "Kernel low-level debugging port"
132 bool "Kernel low-level debugging messages via Alpine UART0"
136 Say Y here if you want kernel low-level debugging support
140 bool "Kernel low-level debugging via asm9260 UART"
161 bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
165 Say Y here if you want kernel low-level debugging support
171 bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
175 Say Y here if you want kernel low-level debugging support
181 bool "Kernel low-level debugging on SAMA5D2 UART1"
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/Linux-v6.6/arch/sparc/kernel/
Dcpumap.c26 /* Increment rover every time level is visited */
34 int level; member
43 int start_index; /* Index of first node of a level in a cpuinfo tree */
44 int end_index; /* Index of last node of a level in a cpuinfo tree */
45 int num_nodes; /* Number of nodes in a level in a cpuinfo tree */
51 /* Offsets into nodes[] for each level of the tree */
52 struct cpuinfo_level level[CPUINFO_LVL_MAX]; member
96 static int cpuinfo_id(int cpu, int level) in cpuinfo_id() argument
100 switch (level) { in cpuinfo_id()
121 * end index, and number of nodes for each level in the cpuinfo tree. The
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/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_z13/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]
/Linux-v6.6/arch/sparc/include/uapi/asm/
Dtraps.h46 #define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
47 #define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
48 #define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
49 #define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
50 #define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
51 #define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
52 #define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
53 #define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
54 #define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
55 #define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
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/Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
Dcache.json111 …"PublicDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from…
114 …"BriefDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from …
117 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a …
120 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p…
123 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t…
126 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
[all …]
/Linux-v6.6/arch/arm64/kernel/
Dcacheinfo.c13 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
24 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument
28 if (level > MAX_CACHE_LEVEL) in get_cache_type()
31 return CLIDR_CTYPE(clidr, level); in get_cache_type()
35 enum cache_type type, unsigned int level) in ci_leaf_init() argument
37 this_leaf->level = level; in ci_leaf_init()
43 unsigned int ctype, level, leaves; in detect_cache_level() local
45 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { in detect_cache_level()
46 ctype = get_cache_type(level); in detect_cache_level()
48 level--; in detect_cache_level()
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/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_zec12/
Dextended.json7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
21 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
35 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in…
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
Dcache.json105 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t…
108 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th…
111 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a …
114 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p…
117 …"PublicDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills f…
120 …"BriefDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills fr…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_z14/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/Linux-v6.6/arch/arm64/boot/dts/rockchip/
Drockchip-pinconf.dtsi23 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
29 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
35 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
41 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
47 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
53 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
59 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
65 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
71 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
77 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_z196/
Dextended.json7 …ption": "A directory write to the Level-1 Data Cache directory where the returned cache line was s…
14 …n": "A directory write to the Level-1 Instruction Cache directory where the returned cache line wa…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
42 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
49 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
56 … "A directory write to the Level-1 Instruction Cache directory where the returned cache line was s…
63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in…
70 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_z15/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/Linux-v6.6/drivers/scsi/
Dscsi_logging.h47 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) \ argument
49 if (unlikely((SCSI_LOG_LEVEL(SHIFT, BITS)) > (LEVEL))) \
56 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) do { } while (0) argument
64 #define SCSI_LOG_ERROR_RECOVERY(LEVEL,CMD) \ argument
65 SCSI_CHECK_LOGGING(SCSI_LOG_ERROR_SHIFT, SCSI_LOG_ERROR_BITS, LEVEL,CMD);
66 #define SCSI_LOG_TIMEOUT(LEVEL,CMD) \ argument
67 SCSI_CHECK_LOGGING(SCSI_LOG_TIMEOUT_SHIFT, SCSI_LOG_TIMEOUT_BITS, LEVEL,CMD);
68 #define SCSI_LOG_SCAN_BUS(LEVEL,CMD) \ argument
69 SCSI_CHECK_LOGGING(SCSI_LOG_SCAN_SHIFT, SCSI_LOG_SCAN_BITS, LEVEL,CMD);
70 #define SCSI_LOG_MLQUEUE(LEVEL,CMD) \ argument
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/Linux-v6.6/tools/power/x86/intel-speed-select/
Disst-display.c84 static void format_and_print_txt(FILE *outf, int level, char *header, in format_and_print_txt() argument
91 if (!level) in format_and_print_txt()
94 if (level == 1) { in format_and_print_txt()
97 for (i = 0; i < level - 1; ++i) in format_and_print_txt()
112 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
119 format_and_print_txt(outf, level, header, value); in format_and_print()
123 if (level == 0) { in format_and_print()
132 for (i = 0; i < level; ++i) in format_and_print()
136 if (last_level == level) in format_and_print()
140 if (last_level != level) in format_and_print()
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
Dl2_cache.json4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
48 …"PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory rea…
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
Dl2_cache.json4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
/Linux-v6.6/arch/x86/kvm/mmu/
Dtdp_iter.c9 * Recalculates the pointer to the SPTE for the current GFN and level and
14 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
15 SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
27 iter->level = iter->root_level; in tdp_iter_restart()
29 iter->gfn = gfn_round_for_level(iter->next_last_level_gfn, iter->level); in tdp_iter_restart()
42 if (WARN_ON_ONCE(!root || (root->role.level < 1) || in tdp_iter_start()
43 (root->role.level > PT64_ROOT_MAX_LEVEL))) { in tdp_iter_start()
49 iter->root_level = root->role.level; in tdp_iter_start()
58 * Given an SPTE and its level, returns a pointer containing the host virtual
62 tdp_ptep_t spte_to_child_pt(u64 spte, int level) in spte_to_child_pt() argument
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