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/Linux-v6.1/Documentation/driver-api/surface_aggregator/clients/
Ddtx.rst39 * **Latch:**
55 Latch States
58 The latch mechanism has two major states: *open* and *closed*. In the
62 The latch can additionally be locked and, correspondingly, unlocked, which
66 documentation for the detachment procedure below. By default, the latch is
82 instructions/commands. In case the latch is unlocked, the led will flash
83 green. If the latch has been locked, the led will be solid red
93 - If the latch is unlocked, the EC will open the latch and the clipboard
98 - If the latch is locked, the EC will *not* open the latch, meaning the
111 latch, after which the user can separate clipboard and base.
[all …]
/Linux-v6.1/include/linux/mfd/abx500/
Dab8500.h74 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
83 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
89 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
98 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
107 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
116 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
125 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
134 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
143 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
152 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dgpio-eic-sprd.txt6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
19 The EIC-latch sub-module is used to latch some special power down signals
20 and generate interrupts, since the EIC-latch does not depend on the APB
33 "sprd,sc9860-eic-latch",
59 compatible = "sprd,sc9860-eic-latch";
/Linux-v6.1/drivers/clk/ti/
Dmux.c81 ti_clk_latch(&mux->reg, mux->latch); in ti_clk_mux_set_parent()
125 s8 latch, u8 clk_mux_flags, u32 *table) in _register_mux() argument
146 mux->latch = latch; in _register_mux()
175 s32 latch = -EINVAL; in of_mux_clk_setup() local
194 of_property_read_u32(node, "ti,latch-bit", &latch); in of_mux_clk_setup()
211 flags, &reg, shift, mask, latch, clk_mux_flags, in of_mux_clk_setup()
235 mux->latch = -EINVAL; in ti_clk_build_component_mux()
/Linux-v6.1/arch/arm/mach-pxa/
Dpcm990_baseboard.h46 #define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
118 #define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
119 #define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
120 #define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
160 #define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
161 #define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
162 #define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
163 #define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
Dregs-uart.h24 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
25 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
40 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
41 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
56 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
57 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
75 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
76 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
104 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
/Linux-v6.1/arch/sh/include/mach-common/mach/
Durquell.h60 #define LATCHCR_OFS 0x3000 /* Latch control register */
61 #define LATCUAR_OFS 0x3010 /* Latch upper address register */
62 #define LATCLAR_OFS 0x3012 /* Latch lower address register */
63 #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
64 #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
/Linux-v6.1/drivers/tty/serial/8250/
D8250_uniphier.c21 * - Divisor latch at 9, no divisor latch access bit
30 /* Divisor Latch Register */
110 /* Divisor latch access bit does not exist. */ in uniphier_serial_out()
144 * This hardware does not have the divisor latch access bit.
145 * The divisor latch register exists at different address.
/Linux-v6.1/kernel/time/
Dclockevents.c32 static u64 cev_delta2ns(unsigned long latch, struct clock_event_device *evt, in cev_delta2ns() argument
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
44 * not equal latch, we know that the above shift overflowed. in cev_delta2ns()
46 if ((clc >> evt->shift) != (u64)latch) in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
62 * we would end up with a latch value larger than the upper in cev_delta2ns()
79 * clockevents_delta2ns - Convert a latch value (device ticks) to nanoseconds
80 * @latch: value to convert
83 * Math helper, returns latch value converted to nanoseconds (bound checked)
85 u64 clockevent_delta2ns(unsigned long latch, struct clock_event_device *evt) in clockevent_delta2ns() argument
[all …]
/Linux-v6.1/arch/sh/include/asm/
Dsmc37c93x.h67 #define UART_DLL 0x0 /* Divisor Latch (LS) */
68 #define UART_DLM 0x2 /* Divisor Latch (MS) */
88 /* Alias for Divisor Latch Register */
127 #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Darmada3700-xtal-clock.txt4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
/Linux-v6.1/drivers/gpio/
Dgpio-eic-sprd.c67 * debounce EIC, latch EIC, async EIC and sync EIC,
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
107 "eic-debounce", "eic-latch", "eic-async",
454 * The debounce EIC and latch EIC can only support level trigger, so we in sprd_eic_toggle_trigger()
552 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async in sprd_eic_irq_handler()
661 .compatible = "sprd,sc9860-eic-latch",
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power8/
Dpipeline.json269 "BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
275 "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
276 "PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
281 "BriefDescription": "Cycles run latch is set and core is in ST mode",
/Linux-v6.1/arch/powerpc/platforms/powermac/
Dtime.c53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
195 /* set the latch to `count' */ in via_calibrate_decr()
/Linux-v6.1/arch/arm/mach-s3c/
Dh1940.h30 /* SD layer latch */
41 /* CPU layer latch */
/Linux-v6.1/include/linux/
Dseqlock.h638 * Latch sequence counters (seqcount_latch_t)
666 * raw_read_seqcount_latch() - pick even/odd latch data copy
699 * raw_write_seqcount_latch() - redirect latch readers to even/odd copy
702 * The latch technique is a multiversion concurrency control method that allows
709 * latch allows the same for non-atomic updates. The trade-off is doubling the
726 * void latch_modify(struct latch_struct *latch, ...)
729 * latch->seq.sequence++;
732 * modify(latch->data[0], ...);
735 * latch->seq.sequence++;
738 * modify(latch->data[1], ...);
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power10/
Dothers.json60 "BriefDescription": "Cycles when at least one thread has the run latch set."
70 "BriefDescription": "Cycles when the run latch is set for all threads."
115 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
270 "BriefDescription": "Completed PowerPC instructions gated by the run latch."
Dcache.json25 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
30 …"PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
/Linux-v6.1/drivers/clocksource/
Dtimer-ixp4xx.c48 u32 latch; member
138 val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK; in ixp4xx_set_periodic()
177 * So make sure the latch is the best value with the two least in ixp4xx_timer_register()
180 tmr->latch = DIV_ROUND_CLOSEST(timer_freq, in ixp4xx_timer_register()
Di8253.c55 * jiffies was incremented and the point where we latch the in i8253_read()
59 outb_p(0x00, PIT_MODE); /* latch the count ASAP */ in i8253_read()
63 /* VIA686a test code... reset the latch if count > max + 1 */ in i8253_read()
/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Dfsl-upm-nand.txt6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
/Linux-v6.1/arch/powerpc/boot/
Dns16550.c20 #define UART_DLL 0 /* Out: Divisor Latch Low */
21 #define UART_DLM 1 /* Out: Divisor Latch High */
/Linux-v6.1/Documentation/devicetree/bindings/clock/ti/
Dmux.txt52 - ti,latch-bit : latch the mux value to HW, only needed if the register
/Linux-v6.1/Documentation/w1/slaves/
Dw1_ds2413.rst30 Bit 1: PIOA Output Latch State
32 Bit 3: PIOB Output Latch State
/Linux-v6.1/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml156 Gear of the third delay line for DS for input data latch in data
165 mediatek,latch-ck:
168 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid

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