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/Linux-v5.15/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c128 * A lane is described by the following bitfields:
180 unsigned lane; member
188 .lane = _lane, \
198 .lane = _lane, \
207 /* lane 0 */
212 /* lane 1 */
219 /* lane 2 */
227 /* lane 3 */
234 /* lane 4 */
245 /* lane 5 */
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Dphy-mvebu-a3700-comphy.c52 unsigned int lane; member
61 .lane = _lane, \
75 /* lane 0 */
82 /* lane 1 */
89 /* lane 2 */
104 static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, in mvebu_a3700_comphy_smc() argument
110 arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); in mvebu_a3700_comphy_smc()
123 static int mvebu_a3700_comphy_get_fw_mode(int lane, int port, in mvebu_a3700_comphy_get_fw_mode() argument
134 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_get_fw_mode()
150 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_set_mode() local
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Dphy-armada38x-comphy.c46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
78 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
79 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
82 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
85 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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/Linux-v5.15/drivers/net/dsa/b53/
Db53_serdes.c37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
39 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
42 WARN_ON(lane > 1); in b53_serdes_set_lane()
45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
46 dev->serdes_lane = lane; in b53_serdes_set_lane()
49 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
52 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
59 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
66 u8 lane = b53_serdes_map_lane(dev, port); in b53_serdes_config() local
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/Linux-v5.15/drivers/net/dsa/mv88e6xxx/
Dserdes.c37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
98 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, in mv88e6352_serdes_power() argument
120 int lane, unsigned int mode, in mv88e6352_serdes_pcs_config() argument
169 int lane, struct phylink_link_state *state) in mv88e6352_serdes_pcs_get_state() argument
190 int lane) in mv88e6352_serdes_pcs_an_restart() argument
203 int lane, int speed, int duplex) in mv88e6352_serdes_pcs_link_up() argument
236 int lane = -ENODEV; in mv88e6352_serdes_get_lane() local
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Dserdes.h107 int lane, unsigned int mode,
111 int lane, unsigned int mode,
115 int lane, struct phylink_link_state *state);
117 int lane, struct phylink_link_state *state);
119 int lane, struct phylink_link_state *state);
121 int lane, struct phylink_link_state *state);
123 int lane);
125 int lane);
127 int lane, int speed, int duplex);
129 int lane, int speed, int duplex);
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/Linux-v5.15/drivers/phy/tegra/
Dxusb.c109 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
112 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
120 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
122 dev_err(dev, "invalid function \"%s\" for lane \"%pOFn\"\n", in tegra_xusb_lane_parse_dt()
127 lane->function = err; in tegra_xusb_lane_parse_dt()
135 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
137 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
185 struct phy *lane; in tegra_xusb_pad_register() local
193 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
202 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
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Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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Dxusb.h54 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
62 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
64 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
75 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
77 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
85 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
87 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
104 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
106 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
114 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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Dxusb-tegra210.c447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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Dxusb-tegra186.c308 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
315 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
318 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
320 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
460 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
462 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
464 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
501 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
503 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_wake()
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/Linux-v5.15/drivers/phy/
Dphy-xgene.c267 /* PHY lane CSR accessing from SDS indirectly */
519 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
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/Linux-v5.15/Documentation/devicetree/bindings/media/
Dvideo-interfaces.yaml162 # Assume up to 9 physical lane indices
165 An array of physical data lane indexes. Position of an entry determines
166 the logical lane number, while the value of an entry indicates physical
167 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
168 assuming the clock lane is on hardware lane 0. If the hardware does not
169 support lane reordering, monotonically incremented values shall be used
171 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
175 # Assume up to 9 physical lane indices
178 Physical clock lane index. Position of an entry determines the logical
179 lane number, while the value of an entry indicates physical lane, e.g. for
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/Linux-v5.15/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c238 int pre_emphasis, int lane) in analogix_dp_set_lane_lane_pre_emphasis() argument
240 switch (lane) { in analogix_dp_set_lane_lane_pre_emphasis()
261 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
269 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
289 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
291 PRE_EMPHASIS_LEVEL_0, lane); in analogix_dp_link_start()
315 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
316 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
327 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
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/Linux-v5.15/drivers/phy/xilinx/
Dphy-zynqmp.c29 * Lane Registers
151 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
152 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
153 #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
154 #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
155 #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
156 #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
157 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
158 #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c277 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dpcd_set_link_settings()
287 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dpcd_set_link_settings()
342 uint32_t lane; in dpcd_set_lt_pattern_and_lane_settings() local
378 for (lane = 0; lane < in dpcd_set_lt_pattern_and_lane_settings()
379 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
381 dpcd_lane[lane].bits.VOLTAGE_SWING_SET = in dpcd_set_lt_pattern_and_lane_settings()
382 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING); in dpcd_set_lt_pattern_and_lane_settings()
383 dpcd_lane[lane].bits.PRE_EMPHASIS_SET = in dpcd_set_lt_pattern_and_lane_settings()
384 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS); in dpcd_set_lt_pattern_and_lane_settings()
386 dpcd_lane[lane].bits.MAX_SWING_REACHED = in dpcd_set_lt_pattern_and_lane_settings()
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/Linux-v5.15/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
/Linux-v5.15/drivers/thunderbolt/
Dlc.c52 u32 ctrl, lane; in tb_lc_set_port_configured() local
66 /* Resolve correct lane */ in tb_lc_set_port_configured()
68 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
70 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
73 ctrl |= lane; in tb_lc_set_port_configured()
77 ctrl &= ~lane; in tb_lc_set_port_configured()
110 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
124 /* Resolve correct lane */ in tb_lc_set_xdomain_configured()
126 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
128 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
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/Linux-v5.15/include/linux/phy/
Dphy-mipi-dphy.h20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
105 * Time, in picoseconds, for the Data Lane receiver to enable
137 * Lane LP-00 Line state immediately before the HS-0 Line
149 * shall ignore any Data Lane HS transitions, starting from
161 * should ignore any transitions on the Data Lane, following a
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Dphy-dp.h31 * lane 0, used for the transmissions on main link.
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
52 * used by particular lanes. One value per lane.
78 * Flag indicating, whether or not reconfigure lane count to
/Linux-v5.15/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
184 /* Set Lane Control Rate */ in netcp_xgbe_serdes_lane_enable()
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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/Linux-v5.15/drivers/media/platform/omap3isp/
Domap3isp.h26 * @data_lane_shift: Data lane shifter
64 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
65 * @pos: position of the lane
66 * @pol: polarity of the lane
77 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
79 * @clk: Clock lane configuration
112 * @lanecfg: CSI-2 lane configuration
/Linux-v5.15/drivers/phy/rockchip/
Dphy-rockchip-typec.c505 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
511 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
512 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
515 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
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/Linux-v5.15/include/linux/platform_data/media/
Domap4iss.h15 * struct iss_csiphy_lane: CSI2 lane position and polarity
16 * @pos: position of the lane
17 * @pol: polarity of the lane
28 * struct iss_csiphy_lanes_cfg - CSI2 lane configuration
30 * @clk: Clock lane configuration
/Linux-v5.15/drivers/pinctrl/tegra/
Dpinctrl-tegra-xusb.c127 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
299 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinmux_set() local
303 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
305 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_pinmux_set()
306 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
309 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
312 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinmux_set()
313 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
314 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
315 padctl_writel(padctl, value, lane->offset); in tegra_xusb_padctl_pinmux_set()
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