| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | baikal,bt1-l2-ctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
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| /Linux-v5.15/drivers/memory/ |
| D | bt1-l2-ctl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
50 * @L2_WSSTALL: Way-select latency.
51 * @L2_TAGSTALL: Tag latency.
52 * @L2_DATASTALL: Data latency.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
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| /Linux-v5.15/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
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| /Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | metrics.json | 50 …the NTF instruction was a load that missed the L1 and was waiting for the data to return from the …
56 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
62 "BriefDescription": "Stalls due to short latency decimal floating ops.",
63 "MetricExpr": "dfu_stall_cpi - dflong_stall_cpi",
75 "MetricExpr": "dmiss_non_local_stall_cpi - dmiss_remote_stall_cpi",
80 …iefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf…
93 "MetricExpr": "dmiss_l2l3_stall_cpi - dmiss_l2l3_conflict_stall_cpi",
98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
[all …]
|
| D | cache.json | 5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
30 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
40 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on t…
55 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…
70 …was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to …
80 …another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When …
85 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
90 …ecause the NTF instruction was a load that hit on an older store and it was waiting for store data"
100 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | memory.json | 3 …lears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores…
21 "BriefDescription": "Loads with latency value being above 4 .",
34 "BriefDescription": "Loads with latency value being above 8.",
47 "BriefDescription": "Loads with latency value being above 16.",
60 "BriefDescription": "Loads with latency value being above 32.",
73 "BriefDescription": "Loads with latency value being above 64.",
86 "BriefDescription": "Loads with latency value being above 128.",
99 "BriefDescription": "Loads with latency value being above 256.",
112 "BriefDescription": "Loads with latency value being above 512.",
123 …le stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | memory.json | 3 "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
13 "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
33 "PublicDescription": "Loads with latency value being above 4.",
41 "BriefDescription": "Loads with latency value being above 4",
47 "PublicDescription": "Loads with latency value being above 8.",
55 "BriefDescription": "Loads with latency value being above 8",
61 "PublicDescription": "Loads with latency value being above 16.",
69 "BriefDescription": "Loads with latency value being above 16",
75 "PublicDescription": "Loads with latency value being above 32.",
83 "BriefDescription": "Loads with latency value being above 32",
[all …]
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| /Linux-v5.15/tools/arch/x86/include/asm/ |
| D | amd-ibs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include "msr-index.h"
17 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
18 fetch_cnt:16, /* 16-31: instruction fetch count */
19 fetch_lat:16, /* 32-47: instruction fetch latency */
23 ic_miss:1, /* 51: i-cache miss */
25 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
27 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
28 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
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| /Linux-v5.15/arch/x86/include/asm/ |
| D | amd-ibs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include <asm/msr-index.h>
17 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
18 fetch_cnt:16, /* 16-31: instruction fetch count */
19 fetch_lat:16, /* 32-47: instruction fetch latency */
23 ic_miss:1, /* 51: i-cache miss */
25 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
27 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
28 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | vf610.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 next-level-cache = <&L2>;
13 L2: cache-controller@40006000 { label
14 compatible = "arm,pl310-cache";
16 cache-unified;
17 cache-level = <2>;
18 arm,data-latency = <3 3 3>;
19 arm,tag-latency = <2 2 2>;
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /Linux-v5.15/arch/arm/mach-sunxi/ |
| D | headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
18 .arch armv7-a
20 * Enable cluster-level coherency, in preparation for turning on the MMU.
22 * Also enable regional clock gating and L2 data latency settings for
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
43 /* Enable L2, GIC, and Timer regional clock gates */
49 /* L2CTRL: L2 data RAM latency */
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /Linux-v5.15/Documentation/x86/ |
| D | resctrl.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
23 CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2"
31 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps]] /sys/fs/resctrl
36 Enable code/data prioritization in L3 cache allocations.
38 Enable code/data prioritization in L2 cache allocations.
43 L2 and L3 CDP are controlled separately.
47 pseudo-locking is a unique way of using cache control to "pin" or
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | memory.json | 71 …"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions a…
106 …f the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores…
111 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
120 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency…
126 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
135 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency…
141 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
150 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency…
156 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
165 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency…
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| D | skx-metrics.json | 27 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
57 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
63 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
123 … "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
129 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
142 "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
148 "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
154 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
160 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
172 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | icx-metrics.json | 27 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
45 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
51 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
117 … "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
123 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
136 "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
142 "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
148 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
154 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
166 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | clx-metrics.json | 27 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
57 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
63 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
129 … "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
135 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
148 "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
154 "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
160 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
166 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
178 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | memory.json | 3 …"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L…
13 …"PublicDescription": "This event counts speculative cache line split store-address (STA) uops disp…
43 …"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store …
49 …"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store t…
63 …on": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatc…
69 …on": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatc…
141 …following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores…
208 … "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
222 …cription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
289 … "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | memory.json | 30 …lears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores…
48 "BriefDescription": "Loads with latency value being above 4 .",
61 "BriefDescription": "Loads with latency value being above 8.",
74 "BriefDescription": "Loads with latency value being above 16.",
87 "BriefDescription": "Loads with latency value being above 32.",
100 "BriefDescription": "Loads with latency value being above 64.",
113 "BriefDescription": "Loads with latency value being above 128.",
126 "BriefDescription": "Loads with latency value being above 256.",
139 "BriefDescription": "Loads with latency value being above 512.",
150 …le stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
[all …]
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| /Linux-v5.15/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/ |
| D | EventClass.py | 2 # SPDX-License-Identifier: GPL-2.0
18 EVTYPE_PEBS_LL = 2 # PEBS event with load latency info
23 # the size of raw buffer, raw PEBS event with load latency data's
52 # Basic Intel PEBS (Precise Event-based Sampling) event, whose raw buffer
77 # Intel Nehalem and Westmere support PEBS plus Load Latency info which lie
78 # in the four 64 bit words write after the PEBS data:
80 # DLA: Data Linear Address (EIP)
81 # DSE: Data Source Encoding, where the latency happens, hit or miss
82 # in L1/L2/L3 or IO operations
83 # LAT: the actual latency in cycles
|
