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/Linux-v5.10/drivers/isdn/mISDN/
Dlayer1.c94 struct layer1 *l1 = fi->userdata; in l1m_debug() local
103 printk(KERN_DEBUG "%s: %pV\n", dev_name(&l1->dch->dev.dev), &vaf); in l1m_debug()
117 struct layer1 *l1 = fi->userdata; in l1_deact_cnf() local
120 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) in l1_deact_cnf()
121 l1->dcb(l1->dch, HW_POWERUP_REQ); in l1_deact_cnf()
127 struct layer1 *l1 = fi->userdata; in l1_deact_req_s() local
130 mISDN_FsmRestartTimer(&l1->timerX, 550, EV_TIMER_DEACT, NULL, 2); in l1_deact_req_s()
131 test_and_set_bit(FLG_L1_DEACTTIMER, &l1->Flags); in l1_deact_req_s()
137 struct layer1 *l1 = fi->userdata; in l1_power_up_s() local
139 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) { in l1_power_up_s()
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dcache.json3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
9 …"PublicDescription": "L1 instruction TLB refill. This event counts any refill of the instruction L…
12 "BriefDescription": "L1 instruction TLB refill"
15 …L1 data cache refill. This event counts any load or store operation or page table walk access whic…
18 "BriefDescription": "L1 data cache refill"
21 …icDescription": "L1 data cache access. This event counts any load or store operation or page table…
24 "BriefDescription": "L1 data cache access"
27 …"PublicDescription": "L1 data TLB refill. This event counts any refill of the data L1 TLB from the…
30 "BriefDescription": "L1 data TLB refill"
[all …]
/Linux-v5.10/Documentation/networking/
Dtls-offload-layers.svg1 …l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.82812…
/Linux-v5.10/security/selinux/ss/
Dmls_types.h30 static inline int mls_level_eq(struct mls_level *l1, struct mls_level *l2) in mls_level_eq() argument
32 return ((l1->sens == l2->sens) && in mls_level_eq()
33 ebitmap_cmp(&l1->cat, &l2->cat)); in mls_level_eq()
36 static inline int mls_level_dom(struct mls_level *l1, struct mls_level *l2) in mls_level_dom() argument
38 return ((l1->sens >= l2->sens) && in mls_level_dom()
39 ebitmap_contains(&l1->cat, &l2->cat, 0)); in mls_level_dom()
42 #define mls_level_incomp(l1, l2) \ argument
43 (!mls_level_dom((l1), (l2)) && !mls_level_dom((l2), (l1)))
45 #define mls_level_between(l1, l2, l3) \ argument
46 (mls_level_dom((l1), (l2)) && mls_level_dom((l3), (l1)))
/Linux-v5.10/arch/sparc/kernel/
Drtrap_64.S62 andn %l1, %o0, %l1
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
87 and %l1, %l4, %l4
88 andn %l1, %l4, %l1
96 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 and %l1, %l4, %l4
99 andn %l1, %l4, %l1
115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
118 and %l1, %l4, %l4
119 andn %l1, %l4, %l1
[all …]
Dhead_64.S169 mov (1b - prom_peer_name), %l1
170 sub %l0, %l1, %l1
174 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
184 mov (1b - prom_root_node), %l1
185 sub %l0, %l1, %l1
186 stw %l4, [%l1]
188 mov (1b - prom_getprop_name), %l1
191 sub %l0, %l1, %l1
198 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
212 mov (1b - prom_finddev_name), %l1
[all …]
Dentry.S63 * This code cannot touch registers %l0 %l1 and %l2
162 jmp %l1
437 ld [%l1], %l5
448 mov %l1, %o1
468 mov %l1, %o1
488 ld [%l1], %o1
500 ld [%l1], %o1
516 mov %l1, %o1
528 cmp %l1, %l5
532 cmp %l1, %l5
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/Linux-v5.10/arch/c6x/lib/
Dcsum_64plus.S50 || ADD .L1 A16,A9,A9
63 || MVK .L1 1,A2
73 ADD .L1 A16,A9,A9
76 || ADD .L1 A8,A9,A9
83 ZERO .L1 A7
115 || ZERO .L1 A7
202 || ADD .L1 A3,A5,A5
292 MV .L1 A0,A3
309 MVK .L1 2,A0
310 AND .L1 A4,A0,A0
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/Linux-v5.10/Documentation/virt/kvm/
Drunning-nested-guests.rst17 | L1 (Guest Hypervisor) |
31 - L1 – level-1 guest; a VM running on L0; also called the "guest
34 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
43 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
47 L1, and L2) for all architectures; and will largely focus on
146 able to start an L1 guest with::
173 2. The guest hypervisor (L1) must be provided with the ``sie`` CPU
177 3. Now the KVM module can be loaded in the L1 (guest hypervisor)::
185 Migrating an L1 guest, with a *live* nested guest in it, to another
189 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
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/Linux-v5.10/arch/c6x/include/uapi/asm/
Dswab.h15 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swab16()
21 asm("swap4 .l1 %0,%0\n" in __c6x_swab32()
22 "swap2 .l1 %0,%0\n" in __c6x_swab32()
30 "|| swap2 .l1 %P0,%p0\n" in __c6x_swab64()
31 " swap4 .l1 %p0,%p0\n" in __c6x_swab64()
32 " swap4 .l1 %P0,%P0\n" in __c6x_swab64()
39 asm("swap2 .l1 %0,%0\n" : "+a"(val)); in __c6x_swahw32()
45 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swahb32()
/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
Dmemory.json57 "BriefDescription": "L1 DTLB Miss or Reload off all sizes.",
63 "BriefDescription": "L1 DTLB Miss of a page of 1G size.",
69 "BriefDescription": "L1 DTLB Miss of a page of 2M size.",
75 "BriefDescription": "L1 DTLB Miss of a page of 32K size.",
81 "BriefDescription": "L1 DTLB Miss of a page of 4K size.",
87 "BriefDescription": "L1 DTLB Reload of a page of 1G size.",
93 "BriefDescription": "L1 DTLB Reload of a page of 2M size.",
99 "BriefDescription": "L1 DTLB Reload of a page of 32K size.",
105 "BriefDescription": "L1 DTLB Reload of a page of 4K size.",
/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen2/
Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
Dbranch.json5 "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)."
26 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
32 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. Instruction fetche…
38 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. Instruction fetche…
44 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. Instruction fetche…
/Linux-v5.10/arch/sparc/lib/
Dxor.S370 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
390 xor %l3, %l1, %l3
418 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
431 xor %l1, %i5, %l1
433 xor %o3, %l1, %o3
437 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
449 xor %l1, %i5, %l1
451 xor %o3, %l1, %o3
482 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
490 xor %l1, %g3, %l1
[all …]
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dsdm660.dtsi49 L1_I_100: l1-icache {
52 L1_D_100: l1-dcache {
64 L1_I_101: l1-icache {
67 L1_D_101: l1-dcache {
79 L1_I_102: l1-icache {
82 L1_D_102: l1-dcache {
94 L1_I_103: l1-icache {
97 L1_D_103: l1-dcache {
113 L1_I_0: l1-icache {
116 L1_D_0: l1-dcache {
[all …]
/Linux-v5.10/drivers/pci/pcie/
Daspm.c3 * Enable PCIe link L0s/L1 state and Clock Power Management
31 #define ASPM_STATE_L1 (4) /* L1 state */
32 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
46 u32 l1; /* L1 latency (nsec) */ member
115 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
320 /* Convert L1 latency encoding to ns */
330 /* Convert L1 acceptable latency encoding to ns */
[all …]
/Linux-v5.10/arch/powerpc/include/asm/
Dsecurity_features.h45 // The L1-D cache can be flushed with ori r30,r30,0
48 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
57 // Entries in L1-D are private to a SMT thread
71 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
74 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
89 // The L1-D cache should be flushed when entering the kernel
92 // The L1-D cache should be flushed after user accesses from the kernel
Dvdso_datapage.h69 __u32 dcache_size; /* L1 d-cache size 0x60 */
70 __u32 dcache_line_size; /* L1 d-cache line size 0x64 */
71 __u32 icache_size; /* L1 i-cache size 0x68 */
72 __u32 icache_line_size; /* L1 i-cache line size 0x6C */
77 __u32 dcache_block_size; /* L1 d-cache block size */
78 __u32 icache_block_size; /* L1 i-cache block size */
79 __u32 dcache_log_block_size; /* L1 d-cache log block size */
80 __u32 icache_log_block_size; /* L1 i-cache log block size */
/Linux-v5.10/arch/arm/mm/
Dproc-xsc3.S41 * The cache line size of the L1 I, L1 D and unified L2 cache.
46 * The size of the L1 D cache.
62 * This macro cleans and invalidates the entire L1 D cache.
68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/regulator/
Dqcom,smd-rpm-regulator.yaml29 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
32 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
36 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6,
40 For pm8994, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
44 For pm8998, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2,
48 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22,
51 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
53 For pma8084, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
61 For pms405, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylake/
Dcache.json43 …"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software pref…
49 …"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches t…
93 …"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software pref…
99 …"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches t…
149 … "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
163 …ds-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not …
174 …ds-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not…
485 …": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This eve…
491 "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
521 …escription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
[all …]
/Linux-v5.10/arch/hexagon/include/asm/
Dmmu_context.h58 int l1; in switch_mm() local
65 for (l1 = MIN_KERNEL_SEG; l1 <= max_kernel_seg; l1++) in switch_mm()
66 next->pgd[l1] = init_mm.pgd[l1]; in switch_mm()
/Linux-v5.10/arch/sparc/include/asm/
Dxor_32.h33 "xor %%g5, %%l1, %%g5\n\t" in sparc_2()
46 "l0", "l1", "l2", "l3", "l4", "l5"); in sparc_2()
72 "xor %%g5, %%l1, %%g5\n\t" in sparc_3()
83 "xor %%g5, %%l1, %%g5\n\t" in sparc_3()
96 "l0", "l1", "l2", "l3", "l4", "l5"); in sparc_3()
123 "xor %%g5, %%l1, %%g5\n\t" in sparc_4()
135 "xor %%g5, %%l1, %%g5\n\t" in sparc_4()
146 "xor %%g5, %%l1, %%g5\n\t" in sparc_4()
159 "l0", "l1", "l2", "l3", "l4", "l5"); in sparc_4()
187 "xor %%g5, %%l1, %%g5\n\t" in sparc_5()
[all …]
/Linux-v5.10/arch/arc/kernel/
Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implies both L2 and L1 active
167 ; need to check STATUS32_L2 to determine if L1 was active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
335 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
[all …]

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