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/Linux-v6.1/Documentation/devicetree/bindings/reset/
Dstarfive,jh7100-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 SoC Reset Controller
10 - Emil Renner Berthing <kernel@esmil.dk>
15 - starfive,jh7100-reset
20 "#reset-cells":
24 - compatible
25 - reg
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/Linux-v6.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
12 compatible = "starfive,jh7100";
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
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/Linux-v6.1/drivers/reset/
Dreset-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7100 SoC
10 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/starfive-jh7100.h>
32 * Most reset lines have their status inverted so a 0 bit in the STATUS
53 /* protect registers against concurrent read-modify-write */
70 void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64); in jh7100_reset_update()
71 void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); in jh7100_reset_update()
80 spin_lock_irqsave(&data->lock, flags); in jh7100_reset_update()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += hisilicon/
4 obj-$(CONFIG_ARCH_STI) += sti/
5 obj-$(CONFIG_ARCH_TEGRA) += tegra/
6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
10 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Pin Controller
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
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/Linux-v6.1/drivers/pinctrl/starfive/
Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7100 SoC
17 #include <linux/reset.h>
23 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
26 #include "../pinctrl-utils.h"
30 #define DRIVER_NAME "pinctrl-starfive"
33 * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
34 * https://github.com/starfive-tech/JH7100_Docs
45 * The following 32-bit registers come in pairs, but only the offset of the
46 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
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/Linux-v6.1/drivers/tty/serial/8250/
D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/reset.h>
72 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
76 value |= d->msr_mask_on; in dw8250_modify_msr()
77 value &= ~d->msr_mask_off; in dw8250_modify_msr()
95 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
96 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
101 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
106 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
110 while (tries--) { in dw8250_check_lcr()
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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