Searched +full:j721e +full:- +full:pcie +full:- +full:ep (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"8 title: TI J721E PCI EP (PCIe Wrapper)11 - Kishon Vijay Abraham I <kishon@ti.com>14 - $ref: "cdns-pcie-ep.yaml#"19 - const: ti,j721e-pcie-ep20 - description: PCIe EP controller in AM64[all …]
1 // SPDX-License-Identifier: GPL-2.03 * pci-j721e - PCIe controller driver for TI's J721E SoCs5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com24 #include "pcie-cadence.h"77 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument79 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()82 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument85 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()88 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument90 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o3 obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o4 obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o5 obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o6 obj-$(CONFIG_PCI_J721E) += pci-j721e.o
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for J721E SoC Family Main Domain peripherals5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/phy/phy-ti.h>9 #include <dt-bindings/mux/mux.h>10 #include <dt-bindings/mux/ti-serdes.h>13 cmn_refclk: clock-cmnrefclk {14 #clock-cells = <0>;15 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/9 serdes_refclk: serdes-refclk {10 #clock-cells = <0>;11 compatible = "fixed-clock";17 compatible = "mmio-sram";19 #address-cells = <1>;20 #size-cells = <1>;23 atf-sram@0 {28 scm_conf: scm-conf@100000 {[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/phy/phy-cadence.h>9 #include <dt-bindings/phy/phy-ti.h>12 serdes_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;21 compatible = "mmio-sram";23 #address-cells = <1>;[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
