| /Linux-v6.6/arch/arm64/include/asm/ |
| D | tlbflush.h | 95 * the level at which the invalidation must take place. If the level is
96 * wrong, no invalidation may take place. In the case where the level
98 * perform a non-hinted invalidation.
100 * For Stage-2 invalidation, use the level values provided to that effect
163 * TLB Invalidation
166 * This header file implements the low-level TLB invalidation routines
169 * Every invalidation operation uses the following template:
173 * DSB ISH // Ensure the TLB invalidation has completed
178 * The following functions form part of the "core" TLB invalidation API,
208 * Next, we have some undocumented invalidation routines that you probably
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| D | kvm_pgtable.h | 218 * TLB invalidation.
370 * to freeing and therefore no TLB invalidation is performed.
406 * TLB invalidation is performed for each page-table entry cleared during the
465 * to freeing and therefore no TLB invalidation is performed.
476 * freeing and therefore no TLB invalidation is performed.
493 * invalidation or CMOs are performed.
568 * TLB invalidation is performed for each page-table entry cleared during the
580 * without TLB invalidation.
644 * TLB invalidation is performed after updating the entry. Software bits cannot
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| /Linux-v6.6/drivers/infiniband/ulp/rtrs/ |
| D | README | 54 The procedure is the default behaviour of the driver. This invalidation and
165 the user header, flags (specifying if memory invalidation is necessary) and the
169 attaches an invalidation message if requested and finally an "empty" rdma
176 or in case client requested invalidation:
184 the user header, flags (specifying if memory invalidation is necessary) and the
190 attaches an invalidation message if requested and finally an "empty" rdma
201 or in case client requested invalidation:
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| /Linux-v6.6/drivers/iommu/intel/ |
| D | dmar.c | 1217 return "Context-cache Invalidation"; in qi_type_string()
1219 return "IOTLB Invalidation"; in qi_type_string()
1221 return "Device-TLB Invalidation"; in qi_type_string()
1223 return "Interrupt Entry Cache Invalidation"; in qi_type_string()
1225 return "Invalidation Wait"; in qi_type_string()
1227 return "PASID-based IOTLB Invalidation"; in qi_type_string()
1229 return "PASID-cache Invalidation"; in qi_type_string()
1231 return "PASID-based Device-TLB Invalidation"; in qi_type_string()
1246 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", in qi_dump_fault()
1249 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", in qi_dump_fault()
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| D | iommu.h | 80 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
81 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
82 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
83 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
84 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
85 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */
338 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
339 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
340 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
430 /* PASID cache invalidation granu */
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| D | pasid.c | 699 * VT-d spec 3.4 table23 states guides for cache invalidation: in intel_pasid_setup_page_snoop_control()
701 * - PASID-selective-within-Domain PASID-cache invalidation in intel_pasid_setup_page_snoop_control()
702 * - PASID-selective PASID-based IOTLB invalidation in intel_pasid_setup_page_snoop_control()
704 * - Global Device-TLB invalidation to affected functions in intel_pasid_setup_page_snoop_control()
706 * - PASID-based Device-TLB invalidation (with S=1 and in intel_pasid_setup_page_snoop_control()
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| /Linux-v6.6/arch/powerpc/include/asm/ |
| D | pnv-ocxl.h | 19 /* Radix Invalidation Control
28 /* Invalidation Criteria
35 /* Invalidation Flag */
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| /Linux-v6.6/arch/arm64/kvm/hyp/nvhe/ |
| D | tlb.c | 26 * being either ish or nsh, depending on the invalidation in __tlb_switch_to_guest()
98 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
101 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
150 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
153 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa_nsh()
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| /Linux-v6.6/arch/arm64/kvm/hyp/vhe/ |
| D | tlb.c | 101 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
104 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
133 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
136 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa_nsh()
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| /Linux-v6.6/arch/arm/mach-versatile/ |
| D | dcscb_setup.S | 20 * A15/A7 may not require explicit L2 invalidation on reset, dependent
23 * or invalidation is not required.
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| /Linux-v6.6/Documentation/filesystems/caching/ |
| D | netfs-api.rst | 36 (8) Data file invalidation
39 (11) Page release and invalidation
285 The read operation will fail with ESTALE if invalidation occurred whilst the
302 Data File Invalidation
319 This increases the invalidation counter in the cookie to cause outstanding
324 Invalidation runs asynchronously in a worker thread so that it doesn't block
427 Page Release and Invalidation
442 Page release and page invalidation should also wait for any mark left on the
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| /Linux-v6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_tlb.c | 17 * HW architecture suggest typical invalidation time at 40us,
25 * On Xe_HP the TLB invalidation registers are located at the same MMIO offsets
99 "%s TLB invalidation did not complete in %ums!\n", in mmio_invalidate_full()
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| /Linux-v6.6/drivers/cxl/ |
| D | Kconfig | 133 to invalidate caches when those events occur. If that invalidation
135 invalidation failure are due to the CPU not providing a cache
136 invalidation mechanism. For example usage of wbinvd is restricted to
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| /Linux-v6.6/include/linux/ |
| D | memregion.h | 41 * contents while performing the invalidation. It is only exported for
59 WARN_ON_ONCE("CPU cache invalidation required"); in cpu_cache_invalidate_memregion()
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| D | io-pgtable.h | 32 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
33 * single page. IOMMUs that cannot batch TLB invalidation
36 * and defer the invalidation until iommu_iotlb_sync() instead.
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| D | mmu_notifier.h | 43 * a device driver to possibly ignore the invalidation if the
143 * Invalidation of multiple concurrent ranges may be
204 * TLB invalidation.
320 * mmu_interval_set_seq - Save the invalidation sequence
350 * Returns true if an invalidation collided with this critical section, and
366 * and mmu_interval_read_retry(). A return of true indicates an invalidation
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| /Linux-v6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | gmc_v11_0.c | 212 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_flush_vm_hub()
213 * release after invalidation to avoid entering power gated state in gmc_v11_0_flush_vm_hub()
248 * add semaphore release after invalidation, in gmc_v11_0_flush_vm_hub()
254 /* Issue additional private vm invalidation to MMHUB */ in gmc_v11_0_flush_vm_hub()
261 /* Issue private invalidation */ in gmc_v11_0_flush_vm_hub()
263 /* Read back to ensure invalidation is done*/ in gmc_v11_0_flush_vm_hub()
295 * Directly use kiq to do the vm invalidation instead in gmc_v11_0_flush_gpu_tlb()
322 * @inst: is used to select which instance of KIQ to use for the invalidation
391 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_emit_flush_gpu_tlb()
392 * release after invalidation to avoid entering power gated state in gmc_v11_0_emit_flush_gpu_tlb()
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| D | amdgpu_hmm.c | 42 * page table invalidation are completed and we once more see a coherent process
60 * @range: details on the invalidation
97 * @range: details on the invalidation
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| D | gmc_v10_0.c | 251 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v10_0_flush_vm_hub()
252 * release after invalidation to avoid entering power gated state in gmc_v10_0_flush_vm_hub()
300 * add semaphore release after invalidation, in gmc_v10_0_flush_vm_hub()
337 * Directly use kiq to do the vm invalidation instead in gmc_v10_0_flush_gpu_tlb()
375 * corruption if an invalidation happens at the same time as an VA in gmc_v10_0_flush_gpu_tlb()
376 * translation. Avoid this by doing the invalidation from the SDMA in gmc_v10_0_flush_gpu_tlb()
411 * @inst: is used to select which instance of KIQ to use for the invalidation
483 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v10_0_emit_flush_gpu_tlb()
484 * release after invalidation to avoid entering power gated state in gmc_v10_0_emit_flush_gpu_tlb()
512 * add semaphore release after invalidation, in gmc_v10_0_emit_flush_gpu_tlb()
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| /Linux-v6.6/drivers/misc/sgi-gru/ |
| D | grutlbpurge.c | 32 /* ---------------------------------- TLB Invalidation functions --------
88 * General purpose TLB invalidation function. This function scans every GRU in
117 * To help improve the efficiency of TLB invalidation, the GMS data
122 * provide the callbacks for TLB invalidation. The GMS contains:
139 * zero to force a full TLB invalidation. This is fast but will
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| /Linux-v6.6/arch/powerpc/kernel/ |
| D | l2cr_6xx.S | 60 - L2I set to perform a global invalidation
111 /* Before we perform the global invalidation, we must disable dynamic
207 /* Perform a global invalidation */
223 /* Wait for the invalidation to complete */
342 /* Perform a global invalidation */
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| /Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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| /Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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| /Linux-v6.6/drivers/gpu/drm/i915/display/ |
| D | intel_frontbuffer.h | 87 * @origin: which operation caused the invalidation
91 * be invalidated. For ORIGIN_CS any subsequent invalidation will be delayed
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| /Linux-v6.6/arch/arm64/kvm/ |
| D | vmid.c | 65 * flush_pending and issuing a local context invalidation on in flush_context()
67 * invalidation over the inner shareable domain on rollover. in flush_context()
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