Home
last modified time | relevance | path

Searched +full:interrupt +full:- +full:map (Results 1 – 25 of 1045) sorted by relevance

12345678910>>...42

/Linux-v6.6/arch/mips/boot/dts/loongson/
Dls7a-pch.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
[all …]
Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,ls-extirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape External Interrupt Controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
15 LX216xA) support inverting the polarity of certain external interrupt
21 - enum:
22 - fsl,ls1021a-extirq
[all …]
Drenesas,rza1-irqc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 Interrupt Controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17 - NMI edge select.
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/pci/
Dmediatek-pcie.txt4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
[all …]
Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
17 - $ref: /schemas/pci/pci-bus.yaml#
21 const: mediatek,mt7621-pci
25 - description: host-pci bridge registers
26 - description: pcie port 0 RC control registers
[all …]
Dxilinx-versal-cpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
23 - description: CPM system level control and status registers.
24 - description: Configuration space region and bridge registers.
[all …]
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Dralink,rt3883-pci.txt7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
[all …]
Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
[all …]
Dintel,ixp4xx-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 - $ref: /schemas/pci/pci-bus.yaml#
20 - enum:
21 - intel,ixp42x-pci
22 - intel,ixp43x-pci
28 - description: IXP4xx-specific registers
[all …]
Dfaraday,ftpci100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 plain and dual PCI. The plain version embeds a cascading interrupt controller
17 chips interrupt controller.
21 The plain variant has 128MiB of non-prefetchable memory space, whereas the
24 Interrupt map considerations:
26 The "dual" variant will get INT A, B, C, D from the system interrupt controller
27 and should point to respective interrupt in that controller in its interrupt-map.
[all …]
Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
[all …]
Dversatile.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
[all …]
/Linux-v6.6/arch/arm/boot/dts/marvell/
Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
/Linux-v6.6/drivers/net/ethernet/intel/ice/
Dice_irq.c1 // SPDX-License-Identifier: GPL-2.0
9 * ice_init_irq_tracker - initialize interrupt tracker
18 pf->irq_tracker.num_entries = max_vectors; in ice_init_irq_tracker()
19 pf->irq_tracker.num_static = num_static; in ice_init_irq_tracker()
20 xa_init_flags(&pf->irq_tracker.entries, XA_FLAGS_ALLOC); in ice_init_irq_tracker()
24 * ice_deinit_irq_tracker - free xarray tracker
29 xa_destroy(&pf->irq_tracker.entries); in ice_deinit_irq_tracker()
33 * ice_free_irq_res - free a block of resources
41 entry = xa_erase(&pf->irq_tracker.entries, index); in ice_free_irq_res()
46 * ice_get_irq_res - get an interrupt resource
[all …]
/Linux-v6.6/Documentation/core-api/irq/
Dirq-domain.rst2 The irq_domain interrupt number mapping library
7 This is simple when there is only one interrupt controller, but in
8 systems with multiple interrupt controllers the kernel must ensure
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
15 mechanisms as the IRQ core system by modelling their interrupt
16 handlers as irqchips, i.e. in effect cascading interrupt controllers.
18 Here the interrupt number loose all kind of correspondence to
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
21 interrupt controller (i.e. the component actually fireing the
[all …]
/Linux-v6.6/drivers/of/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
13 * device tree to actual irq numbers on an interrupt controller
29 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
30 * @dev: Device node of the device whose interrupt is to be mapped
31 * @index: Index of the interrupt to map
48 * of_irq_find_parent - Given a device node, find its interrupt parent node
51 * Return: A pointer to the interrupt parent node, or NULL if the interrupt
63 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
[all …]
/Linux-v6.6/arch/arm/boot/dts/airoha/
Den7523.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 reserved-memory {
14 #address-cells = <1>;
[all …]
/Linux-v6.6/drivers/gpio/
Dgpio-pcie-idio-24.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES PCIe-IDIO-24 family
6 * This driver supports the following ACCES devices: PCIe-IDIO-24,
7 * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
22 * PLX PEX8311 PCI LCS_INTCSR Interrupt Control/Status
25 * 0: Enable Interrupt Sources (Bit 0)
26 * 1: Enable Interrupt Sources (Bit 1)
27 * 2: Generate Internal PCI Bus Internal SERR# Interrupt
28 * 3: Mailbox Interrupt Enable
29 * 4: Power Management Interrupt Enable
[all …]
/Linux-v6.6/drivers/pci/msi/
Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
17 * pci_enable_msi() - Enable MSI interrupt mode on device
21 * allocate a single interrupt vector. On success, the allocated vector
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
44 * free earlier allocated interrupt vectors, and restore INTx emulation.
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
[all …]
/Linux-v6.6/drivers/irqchip/
Dirq-ingenic-tcu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
11 #include <linux/mfd/ingenic-tcu.h>
17 struct regmap *map; member
26 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_tcu_intc_cascade()
29 struct regmap *map = gc->private; in ingenic_tcu_intc_cascade() local
34 regmap_read(map, TCU_REG_TFR, &irq_reg); in ingenic_tcu_intc_cascade()
35 regmap_read(map, TCU_REG_TMR, &irq_mask); in ingenic_tcu_intc_cascade()
52 struct regmap *map = gc->private; in ingenic_tcu_gc_unmask_enable_reg() local
53 u32 mask = d->mask; in ingenic_tcu_gc_unmask_enable_reg()
[all …]

12345678910>>...42