| /Linux-v6.1/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
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| D | loongson64-2k1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
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| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,ls-extirq.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape External Interrupt Controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
15 LX216xA) support inverting the polarity of certain external interrupt
21 - enum:
22 - fsl,ls1021a-extirq
[all …]
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| D | renesas,rza1-irqc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 Interrupt Controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17 - NMI edge select.
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
[all …]
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| D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
17 - $ref: /schemas/pci/pci-bus.yaml#
21 const: mediatek,mt7621-pci
25 - description: host-pci bridge registers
26 - description: pcie port 0 RC control registers
[all …]
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| D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
23 - description: CPM system level control and status registers.
24 - description: Configuration space region and bridge registers.
[all …]
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| D | xilinx-pcie.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
[all …]
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| D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
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| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
[all …]
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| D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
15 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
20 - enum:
23 - brcm,iproc-pcie
[all …]
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| D | intel,ixp4xx-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 - $ref: /schemas/pci/pci-bus.yaml#
20 - enum:
21 - intel,ixp42x-pci
22 - intel,ixp43x-pci
28 - description: IXP4xx-specific registers
[all …]
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| D | faraday,ftpci100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 plain and dual PCI. The plain version embeds a cascading interrupt controller
17 chips interrupt controller.
21 The plain variant has 128MiB of non-prefetchable memory space, whereas the
24 Interrupt map considerations:
26 The "dual" variant will get INT A, B, C, D from the system interrupt controller
27 and should point to respective interrupt in that controller in its interrupt-map.
[all …]
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| D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
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| D | versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
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| D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
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| D | en7523.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 reserved-memory {
14 #address-cells = <1>;
[all …]
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| D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
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| D | armada-385.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
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| D | armada-380.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
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| /Linux-v6.1/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
7 This is simple when there is only one interrupt controller, but in
8 systems with multiple interrupt controllers the kernel must ensure
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
15 mechanisms as the IRQ core system by modelling their interrupt
16 handlers as irqchips, i.e. in effect cascading interrupt controllers.
18 Here the interrupt number loose all kind of correspondence to
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
21 interrupt controller (i.e. the component actually fireing the
[all …]
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| /Linux-v6.1/drivers/of/ |
| D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
13 * device tree to actual irq numbers on an interrupt controller
29 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
30 * @dev: Device node of the device whose interrupt is to be mapped
31 * @index: Index of the interrupt to map
48 * of_irq_find_parent - Given a device node, find its interrupt parent node
51 * Return: A pointer to the interrupt parent node, or NULL if the interrupt
63 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
[all …]
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| /Linux-v6.1/drivers/dma/ipu/ |
| D | ipu_irq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma/ipu-dma.h>
20 * Register read / write - shall be inlined by the compiler
24 return __raw_readl(ipu->reg_ipu + reg); in ipu_read_reg()
29 __raw_writel(value, ipu->reg_ipu + reg); in ipu_write_reg()
95 struct ipu_irq_map *map = irq_data_get_irq_chip_data(d); in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
105 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); in ipu_irq_unmask()
109 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_unmask()
110 reg |= (1UL << (map->source & 31)); in ipu_irq_unmask()
[all …]
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| /Linux-v6.1/drivers/irqchip/ |
| D | irq-ingenic-tcu.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
11 #include <linux/mfd/ingenic-tcu.h>
17 struct regmap *map; member
26 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_tcu_intc_cascade()
29 struct regmap *map = gc->private; in ingenic_tcu_intc_cascade() local
34 regmap_read(map, TCU_REG_TFR, &irq_reg); in ingenic_tcu_intc_cascade()
35 regmap_read(map, TCU_REG_TMR, &irq_mask); in ingenic_tcu_intc_cascade()
52 struct regmap *map = gc->private; in ingenic_tcu_gc_unmask_enable_reg() local
53 u32 mask = d->mask; in ingenic_tcu_gc_unmask_enable_reg()
[all …]
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