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/Linux-v6.1/arch/mips/boot/dts/loongson/
Dls7a-pch.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
[all …]
Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,ls-extirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape External Interrupt Controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
15 LX216xA) support inverting the polarity of certain external interrupt
21 - enum:
22 - fsl,ls1021a-extirq
[all …]
Drenesas,rza1-irqc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 Interrupt Controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17 - NMI edge select.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
17 - $ref: /schemas/pci/pci-bus.yaml#
21 const: mediatek,mt7621-pci
25 - description: host-pci bridge registers
26 - description: pcie port 0 RC control registers
[all …]
Dmediatek-pcie.txt4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
[all …]
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Dralink,rt3883-pci.txt7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
[all …]
Dxilinx-pcie.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
[all …]
Dxilinx-versal-cpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
23 - description: CPM system level control and status registers.
24 - description: Configuration space region and bridge registers.
[all …]
Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
15 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
20 - enum:
23 - brcm,iproc-pcie
[all …]
Dversatile.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
[all …]
Dintel,ixp4xx-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 - $ref: /schemas/pci/pci-bus.yaml#
20 - enum:
21 - intel,ixp42x-pci
22 - intel,ixp43x-pci
28 - description: IXP4xx-specific registers
[all …]
/Linux-v6.1/drivers/irqchip/
Dirq-ingenic-tcu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
11 #include <linux/mfd/ingenic-tcu.h>
17 struct regmap *map; member
26 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_tcu_intc_cascade()
29 struct regmap *map = gc->private; in ingenic_tcu_intc_cascade() local
34 regmap_read(map, TCU_REG_TFR, &irq_reg); in ingenic_tcu_intc_cascade()
35 regmap_read(map, TCU_REG_TMR, &irq_mask); in ingenic_tcu_intc_cascade()
52 struct regmap *map = gc->private; in ingenic_tcu_gc_unmask_enable_reg() local
53 u32 mask = d->mask; in ingenic_tcu_gc_unmask_enable_reg() local
[all …]
Dirq-hip04.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2002-2014 ARM Limited.
6 * Copyright (c) 2013-2014 HiSilicon Ltd.
7 * Copyright (c) 2013-2014 Linaro Ltd.
9 * Interrupt architecture for the HIP04 INTC:
11 * o There is one Interrupt Distributor, which receives interrupts
12 * from system devices and sends them to the Interrupt Controllers.
20 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * registers are banked per-cpu for these sources.
39 #include <linux/interrupt.h>
[all …]
Dirq-ls-extirq.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "irq-ls-extirq: " fmt
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 struct irq_fwspec map[MAXIRQ]; member
26 static void ls_extirq_intpcr_rmw(struct ls_extirq_data *priv, u32 mask, in ls_extirq_intpcr_rmw() argument
33 * IRQ descriptors, making sure the read-modify-write is atomic. in ls_extirq_intpcr_rmw()
35 raw_spin_lock(&priv->lock); in ls_extirq_intpcr_rmw()
37 if (priv->big_endian) in ls_extirq_intpcr_rmw()
38 intpcr = ioread32be(priv->intpcr); in ls_extirq_intpcr_rmw()
40 intpcr = ioread32(priv->intpcr); in ls_extirq_intpcr_rmw()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
/Linux-v6.1/arch/powerpc/sysdev/ge/
Dge_pic.c2 * Interrupt handling for GE FPGA based PIC
18 #include <linux/interrupt.h>
40 /* Interrupt Controller Interface Registers */
59 * Interrupt Controller Handling
61 * The interrupt controller handles interrupts for most on board interrupts,
69 * 12 RO Real Time Clock Interrupt Status
70 * 11 RO Temperature Interrupt Status
71 * 10 RO Temperature Critical Interrupt Status
72 * 9 RO Ethernet PHY1 Interrupt Status
73 * 8 RO Ethernet PHY3 Interrupt Status
[all …]
/Linux-v6.1/block/
Dblk-mq-rdma.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/blk-mq.h>
6 #include <linux/blk-mq-rdma.h>
10 * blk_mq_rdma_map_queues - provide a default queue mapping for rdma device
11 * @map: CPU to hardware queue map.
13 * @first_vec: first interrupt vectors to use for queues (usually 0)
16 * interrupt vetors as @set has queues. It will then query it's affinity mask
21 * @set->nr_hw_queues, or @dev does not provide an affinity mask for a
24 void blk_mq_rdma_map_queues(struct blk_mq_queue_map *map, in blk_mq_rdma_map_queues() argument
27 const struct cpumask *mask; in blk_mq_rdma_map_queues() local
[all …]
/Linux-v6.1/drivers/base/regmap/
Dregmap-irq.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/interrupt.h>
24 struct regmap *map; member
59 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
64 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status() local
67 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
71 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
72 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
73 !map->use_single_read; in regmap_irq_can_bulk_read_status()
80 mutex_lock(&d->lock); in regmap_irq_lock()
[all …]
/Linux-v6.1/drivers/pcmcia/
Dpd6729.c2 * Driver for the Cirrus PD6729 PCI-PCMCIA bridge.
16 #include <linux/interrupt.h>
28 MODULE_DESCRIPTION("Driver for the Cirrus PD6729 PCI-PCMCIA bridge");
29 MODULE_AUTHOR("Jun Komuro <komurojun-mbn@nifty.com>");
46 * Specifies the interrupt delivery mode. The default (1) is to use PCI
51 static int irq_mode = 1; /* 0 = ISA interrupt, 1 = PCI interrupt */
55 "interrupt delivery mode. 0 = ISA, 1 = PCI. default is 1");
69 reg += socket->number * 0x40; in indirect_read()
70 port = socket->io_base; in indirect_read()
86 reg = reg + socket->number * 0x40; in indirect_read16()
[all …]
/Linux-v6.1/arch/mips/boot/dts/img/
Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
[all …]

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