Searched +full:interrupt +full:- +full:controller (Results 1 – 25 of 1091) sorted by relevance
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/Linux-v5.4/arch/arm/boot/dts/ |
D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Exynos5410 SoC pin-mux and pin-config device tree source 9 #include <dt-bindings/pinctrl/samsung.h> 13 gpio-controller; 14 #gpio-cells = <2>; 16 interrupt-controller; 17 #interrupt-cells = <2>; 21 gpio-controller; 22 #gpio-cells = <2>; 24 interrupt-controller; [all …]
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D | exynos5260-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device 12 #include <dt-bindings/pinctrl/samsung.h> 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 24 gpio-controller; 25 #gpio-cells = <2>; [all …]
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D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device 12 #include <dt-bindings/pinctrl/samsung.h> 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 24 gpio-controller; 25 #gpio-cells = <2>; [all …]
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D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device 12 #include <dt-bindings/pinctrl/samsung.h> 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 24 gpio-controller; 25 #gpio-cells = <2>; [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/ |
D | mrvl,intc.txt | 1 * Marvell MMP Interrupt controller 4 - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or 5 "mrvl,mmp2-mux-intc" 6 - reg : Address and length of the register set of the interrupt controller. 7 If the interrupt controller is intc, address and length means the range 8 of the whole interrupt controller. If the interrupt controller is mux-intc, 9 address and length means one register. Since address of mux-intc is in the 10 range of intc. mux-intc is secondary interrupt controller. 11 - reg-names : Name of the register set of the interrupt controller. It's 12 only required in mux-intc interrupt controller. [all …]
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D | ti,c64x+megamod-pic.txt | 1 C6X Interrupt Chips 2 ------------------- 4 * C64X+ Core Interrupt Controller 6 The core interrupt controller provides 16 prioritized interrupts to the 8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt 12 -------------------- 13 - compatible: Should be "ti,c64x+core-pic"; 14 - #interrupt-cells: <1> 16 Interrupt Specifier Definition 17 ------------------------------ [all …]
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D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller 3 This interrupt controller hardware is a second level interrupt controller that 4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based 7 Such an interrupt controller has the following hardware design: 9 - outputs multiple interrupts signals towards its interrupt controller parent 11 - controls how some of the interrupts will be flowing, whether they will 12 directly output an interrupt signal towards the interrupt controller parent, 13 or if they will output an interrupt signal at this 2nd level interrupt 14 controller, in particular for UARTs 16 - has one 32-bit enable word and one 32-bit status word [all …]
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D | samsung,exynos4210-combiner.txt | 1 * Samsung Exynos Interrupt Combiner Controller 3 Samsung's Exynos4 architecture includes a interrupt combiner controller which 4 can combine interrupt sources as a group and provide a single interrupt request 5 for the group. The interrupt request from each group are connected to a parent 6 interrupt controller, such as GIC in case of Exynos4210. 8 The interrupt combiner controller consists of multiple combiners. Up to eight 9 interrupt sources can be connected to a combiner. The combiner outputs one 10 combined interrupt for its eight interrupt sources. The combined interrupt 11 is usually connected to a parent interrupt controller. 13 A single node in the device tree is used to describe the interrupt combiner [all …]
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D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers 3 * Main interrupt controller 6 - compatible: shall be "marvell,orion-intc" 7 - reg: base address(es) of interrupt registers starting with CAUSE register 8 - interrupt-controller: identifies the node as an interrupt controller 9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1 11 The interrupt sources map to the corresponding bits in the interrupt 13 - 0 maps to bit 0 of first base address, 14 - 1 maps to bit 1 of first base address, 15 - 32 maps to bit 0 of second base address, and so on. [all …]
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D | sigma,smp8642-intc.txt | 1 Sigma Designs SMP86xx/SMP87xx secondary interrupt controller 4 - compatible: should be "sigma,smp8642-intc" 5 - reg: physical address of MMIO region 6 - ranges: address space mapping of child nodes 7 - interrupt-controller: boolean 8 - #address-cells: should be <1> 9 - #size-cells: should be <1> 12 - reg: address of registers for this control block 13 - interrupt-controller: boolean 14 - #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt [all …]
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D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller 2 -------------------------------- 4 The Marvell ICU (Interrupt Consolidation Unit) controller is 5 responsible for collecting all wired-interrupt sources in the CP and 6 communicating them to the GIC in the AP, the unit translates interrupt 13 - compatible: Should be "marvell,cp110-icu" 15 - reg: Should contain ICU registers location and length. 17 Subnodes: Each group of interrupt is declared as a subnode of the ICU, 22 - compatible: Should be one of: 23 * "marvell,cp110-icu-nsr" [all …]
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D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller 4 The Abilis TB10x SOC contains a custom interrupt controller. It performs 5 one-to-one mapping of external interrupt sources to CPU interrupts and 9 ------------------- 11 - compatible: Should be "abilis,tb10x-ictl" 12 - reg: specifies physical base address and size of register range. 13 - interrupt-congroller: Identifies the node as an interrupt controller. 14 - #interrupt cells: Specifies the number of cells used to encode an interrupt 15 source connected to this controller. The value shall be 2. 16 - interrupts: Specifies the list of interrupt lines which are handled by [all …]
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D | samsung,s3c24xx-irq.txt | 1 Samsung S3C24XX Interrupt Controllers 3 The S3C24XX SoCs contain a custom set of interrupt controllers providing a 4 varying number of interrupt sources. The set consists of a main- and sub- 5 controller and on newer SoCs even a second main controller. 8 - compatible: Compatible property value should be "samsung,s3c2410-irq" 9 for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. 11 - reg: Physical base address of the controller and length of memory mapped 14 - interrupt-controller : Identifies the node as an interrupt controller 16 - #interrupt-cells : Specifies the number of cells needed to encode an 17 interrupt source. The value shall be 4 and interrupt descriptor shall [all …]
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/Linux-v5.4/arch/arm64/boot/dts/exynos/ |
D | exynos7-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as 12 #include <dt-bindings/pinctrl/samsung.h> 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 interrupt-parent = <&gic>; 21 #interrupt-cells = <2>; 33 gpio-controller; [all …]
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D | exynos5433-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device 12 #include <dt-bindings/pinctrl/samsung.h> 17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \ 24 gpio-controller; 25 #gpio-cells = <2>; 27 interrupt-controller; [all …]
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/Linux-v5.4/drivers/irqchip/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 96 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 217 bool "J-Core integrated AIC" if COMPILE_TEST 221 Support for the J-Core integrated AIC. 231 Enable support for the Renesas Interrupt Controller for external 232 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 235 bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST 239 Enable support for the Renesas Interrupt Controller for external 240 devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs. [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/pinctrl/ |
D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller 4 controller. It controls the input/output settings on the available pads/pins 6 on-chip controllers onto these pads. 9 - compatible: should be one of the following. 10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, 11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, 12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, 13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, 14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, 15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/gpio/ |
D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on 6 Every GPIO controller node must have #gpio-cells property defined, 7 this information will be used to translate gpio-specifiers. 11 The GPIO module usually is connected to the SoC's internal interrupt 12 controller, see bindings/interrupt-controller/interrupts.txt (the 13 interrupt client nodes section) for details how to specify this GPIO 14 module's interrupt. 16 The GPIO module may serve as another interrupt controller (cascaded to 17 the SoC's internal interrupt controller). See the interrupt controller 18 nodes section in bindings/interrupt-controller/interrupts.txt for [all …]
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D | gpio-mxs.txt | 1 * Freescale MXS GPIO controller 3 The Freescale MXS GPIO controller is part of MXS PIN controller. The 6 As the GPIO controller is embedded in the PIN controller and all the 7 GPIO ports share the same IO space with PIN controller, the GPIO node 8 will be represented as sub-nodes of MXS pinctrl node. 11 - compatible : Should be "fsl,<soc>-gpio". The supported SoCs include 13 - interrupts : Should be the port interrupt shared by all 32 pins. 14 - gpio-controller : Marks the device node as a gpio controller. 15 - #gpio-cells : Should be two. The first cell is the pin number and 19 - interrupt-controller: Marks the device node as an interrupt controller. [all …]
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D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller 3 The controller's registers are organized as sets of eight 32-bit 5 interrupt is shared for all of the banks handled by the controller. 9 - compatible: 10 Must be "brcm,brcmstb-gpio" 12 - reg: 14 the brcmstb GPIO controller registers 16 - #gpio-cells: 17 Should be <2>. The first cell is the pin number (within the controller's 19 bit[0]: polarity (0 for active-high, 1 for active-low) [all …]
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D | gpio-eic-sprd.txt | 1 Spreadtrum EIC controller bindings 3 The EIC is the abbreviation of external interrupt controller, which can 6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and 7 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub- 10 The EIC-debounce sub-module provides up to 8 source input signal 12 stable status (millisecond resolution) and a single-trigger mechanism 13 is introduced into this sub-module to enhance the input event detection 14 reliability. In addition, this sub-module's clock can be shut off 19 The EIC-latch sub-module is used to latch some special power down signals 20 and generate interrupts, since the EIC-latch does not depend on the APB [all …]
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/Linux-v5.4/arch/mips/boot/dts/ingenic/ |
D | jz4770.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/jz4770-cgu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 10 cpuintc: interrupt-controller { 11 #address-cells = <0>; 12 #interrupt-cells = <1>; 13 interrupt-controller; 14 compatible = "mti,cpu-interrupt-controller"; 17 intc: interrupt-controller@10001000 { [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/pci/ |
D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings 3 This describes the devicetree bindings for PCIe host controller implemented 6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. 9 Documentation/devicetree/bindings/pci/designware-pcie.txt. 12 - compatible: Should be "socionext,uniphier-pcie". 13 - reg: Specifies offset and length of the register set for the device. 14 According to the reg-names, appropriate register sets are required. 15 - reg-names: Must include the following entries: 16 "dbi" - controller configuration registers 17 "link" - SoC-specific glue layer registers [all …]
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D | aardvark-pci.txt | 1 Aardvark PCIe controller 3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC. 5 The Device Tree node describing an Aardvark PCIe controller must 8 - compatible: Should be "marvell,armada-3700-pcie" 9 - reg: range of registers for the PCIe controller 10 - interrupts: the interrupt line of the PCIe controller 11 - #address-cells: set to <3> 12 - #size-cells: set to <2> 13 - device_type: set to "pci" 14 - ranges: ranges for the PCI memory and I/O regions [all …]
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/Linux-v5.4/arch/arm64/boot/dts/hisilicon/ |
D | hi3670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/hi3670-clock.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "arm,psci-0.2"; 24 #address-cells = <2>; 25 #size-cells = <0>; 27 cpu-map { [all …]
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