Home
last modified time | relevance | path

Searched +full:interrupt +full:- +full:affinity (Results 1 – 25 of 385) sorted by relevance

12345678910>>...16

/Linux-v6.6/kernel/irq/
Dcpuhotplug.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic cpu hotunplug interrupt migration code copied from the
12 #include <linux/interrupt.h>
19 /* For !GENERIC_IRQ_EFFECTIVE_AFF_MASK this looks at general affinity mask */
27 * The cpumask_empty() check is a workaround for interrupt chips, in irq_needs_fixup()
28 * which do not implement effective affinity, but the architecture has in irq_needs_fixup()
29 * enabled the config switch. Use the general affinity mask instead. in irq_needs_fixup()
45 pr_warn("Eff. affinity %*pbl of IRQ %u contains only offline CPUs after offlining CPU %u\n", in irq_needs_fixup()
46 cpumask_pr_args(m), d->irq, cpu); in irq_needs_fixup()
58 const struct cpumask *affinity; in migrate_one_irq() local
[all …]
Dirqdesc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the interrupt descriptor management code. Detailed
7 * information is available in Documentation/core-api/genericirq.rst
13 #include <linux/interrupt.h>
22 * lockdep: we want to handle all irq_desc locks as a single lock-class:
56 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, in alloc_masks()
58 return -ENOMEM; in alloc_masks()
61 if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity, in alloc_masks()
[all …]
Dmanage.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
15 #include <linux/interrupt.h>
50 while (irqd_irq_inprogress(&desc->irq_data)) in __synchronize_hardirq()
53 /* Ok, that indicated we're done: double-check carefully. */ in __synchronize_hardirq()
54 raw_spin_lock_irqsave(&desc->lock, flags); in __synchronize_hardirq()
55 inprogress = irqd_irq_inprogress(&desc->irq_data); in __synchronize_hardirq()
70 raw_spin_unlock_irqrestore(&desc->lock, flags); in __synchronize_hardirq()
77 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
[all …]
Daffinity.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2016-2017 Christoph Hellwig.
6 #include <linux/interrupt.h>
14 affd->nr_sets = 1; in default_calc_sets()
15 affd->set_size[0] = affvecs; in default_calc_sets()
19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
21 * @affd: Description of the affinity requirements
32 * Determine the number of vectors which need interrupt affinities in irq_create_affinity_masks()
37 if (nvecs > affd->pre_vectors + affd->post_vectors) in irq_create_affinity_masks()
38 affvecs = nvecs - affd->pre_vectors - affd->post_vectors; in irq_create_affinity_masks()
[all …]
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
23 * struct msi_ctrl - MSI internal management control structure
28 * than the range due to PCI/multi-MSI.
38 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
48 * msi_alloc_desc - Allocate an initialized msi_desc
51 * @affinity: Optional pointer to an affinity mask array size of @nvec
53 * If @affinity is not %NULL then an affinity array[@nvec] is allocated
54 * and the affinity masks and flags from @affinity are copied.
59 const struct irq_affinity_desc *affinity) in msi_alloc_desc() argument
66 desc->dev = dev; in msi_alloc_desc()
[all …]
Dproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2004 Linus Torvalds, Ingo Molnar
12 #include <linux/interrupt.h>
22 * concurrent free of the interrupt descriptor. remove_proc_entry()
26 * We remove the proc entries first and then delete the interrupt
40 AFFINITY, enumerator
48 struct irq_desc *desc = irq_to_desc((long)m->private); in show_irq_affinity()
52 case AFFINITY: in show_irq_affinity()
54 mask = desc->irq_common_data.affinity; in show_irq_affinity()
56 if (irqd_is_setaffinity_pending(&desc->irq_data)) in show_irq_affinity()
[all …]
Dirqdomain.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
30 bool realloc, const struct irq_affinity_desc *affinity);
52 return fwid->name; in irqchip_fwnode_get_name()
61 * __irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
66 * @pa: Optional user-provided physical address
90 n = kasprintf(GFP_KERNEL, "%s-%d", name, id); in __irq_domain_alloc_fwnode()
103 fwid->type = type; in __irq_domain_alloc_fwnode()
104 fwid->name = n; in __irq_domain_alloc_fwnode()
105 fwid->pa = pa; in __irq_domain_alloc_fwnode()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 # Supports effective affinity mask
30 # Support for delayed migration from interrupt context
38 # Alpha specific irq affinity mechanism
42 # Interrupt injection mechanism
54 # Generic configurable interrupt chip implementation
59 # Generic irq_domain hw <--> linux irq number translation
74 # Support for obsolete non-mapping irq domains
94 # Generic MSI hierarchical interrupt domain support
124 out the interrupt descriptors in a more NUMA-friendly way. )
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/
Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
[all …]
Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller 2
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller 2 is a simple interrupt controller present on
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
[all …]
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
/Linux-v6.6/drivers/pci/msi/
Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
17 * pci_enable_msi() - Enable MSI interrupt mode on device
21 * allocate a single interrupt vector. On success, the allocated vector
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
44 * free earlier allocated interrupt vectors, and restore INTx emulation.
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
[all …]
/Linux-v6.6/include/linux/
Dirq.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Thanks. --rmk
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
[all …]
Dinterrupt.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* interrupt.h */
25 * linux/ioport.h to select the interrupt line behaviour. When
26 * requesting an interrupt without specifying a IRQF_TRIGGER, the
43 * IRQF_SHARED - allow sharing the irq among several devices
44 * IRQF_PROBE_SHARED - set by callers when they expect sharing mismatches to occur
45 * IRQF_TIMER - Flag to mark this interrupt as timer interrupt
46 * IRQF_PERCPU - Interrupt is per cpu
47 * IRQF_NOBALANCING - Flag to exclude this interrupt from irq balancing
48 * IRQF_IRQPOLL - Interrupt is used for polling (only the interrupt that is
[all …]
/Linux-v6.6/drivers/infiniband/hw/hfi1/
Daffinity.c1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
8 #include <linux/interrupt.h>
12 #include "affinity.h"
35 cpumask_clear(&set->mask); in init_cpu_mask_set()
36 cpumask_clear(&set->used); in init_cpu_mask_set()
37 set->gen = 0; in init_cpu_mask_set()
43 if (cpumask_equal(&set->mask, &set->used)) { in _cpu_mask_set_gen_inc()
48 set->gen++; in _cpu_mask_set_gen_inc()
49 cpumask_clear(&set->used); in _cpu_mask_set_gen_inc()
[all …]
/Linux-v6.6/drivers/perf/
Darm_pmu_platform.c1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
[all …]
/Linux-v6.6/Documentation/arch/ia64/
Dirq-redir.rst2 IRQ affinity on IA64 platforms
8 By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
10 that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
14 CPUs. Only the first non-zero bit is taken into account.
21 first non-zero bit is the selected CPU. This format has been kept for
24 Set the delivery mode of interrupt 41 to fixed and route the
38 gives the target CPU mask for the specified interrupt vector. If the CPU
39 mask is preceded by the character "r", the interrupt is redirectable
49 IO-SAPIC interrupts are initialized with CPU#0 as their default target
55 - minimal for an idle task,
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/arm/
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
/Linux-v6.6/lib/
Dcpu_rmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cpu_rmap.c: CPU affinity reverse-map support
8 #include <linux/interrupt.h>
13 * objects with CPU affinities. This can be seen as a reverse-map of
14 * CPU affinity. However, we do not assume that the object affinities
21 * alloc_cpu_rmap - allocate CPU affinity reverse-map
39 rmap = kzalloc(obj_offset + size * sizeof(rmap->obj[0]), flags); in alloc_cpu_rmap()
43 kref_init(&rmap->refcount); in alloc_cpu_rmap()
44 rmap->obj = (void **)((char *)rmap + obj_offset); in alloc_cpu_rmap()
50 * any newly-hotplugged CPUs to have some object assigned. in alloc_cpu_rmap()
[all …]
/Linux-v6.6/block/
Dblk-mq-virtio.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/blk-mq-virtio.h>
9 #include "blk-mq.h"
12 * blk_mq_virtio_map_queues - provide a default queue mapping for virtio device
15 * @first_vec: first interrupt vectors to use for queues (usually 0)
18 * interrupt vectors as @set has queues. It will then query the vector
19 * corresponding to each queue for it's affinity mask and built queue mapping
20 * that maps a queue to the CPUs that have irq affinity for the corresponding
29 if (!vdev->config->get_vq_affinity) in blk_mq_virtio_map_queues()
32 for (queue = 0; queue < qmap->nr_queues; queue++) { in blk_mq_virtio_map_queues()
[all …]
/Linux-v6.6/drivers/irqchip/
Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
14 #include <linux/interrupt.h>
47 u8 affinity[MAX_WORDS * IRQS_PER_WORD]; member
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
94 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
100 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
127 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
129 cpu = intc->cpus[0]; in bcm7038_l1_irq_handle()
[all …]
/Linux-v6.6/arch/powerpc/sysdev/xics/
Dxics-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/interrupt.h>
60 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); in xics_update_irq_servers()
68 /* Global interrupt distribution server is specified in the last in xics_update_irq_servers()
69 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last in xics_update_irq_servers()
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver; in xics_set_cpu_giq()
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", in xics_set_cpu_giq()
107 icp_ops->set_priority(LOWEST_PRIORITY); in xics_setup_cpu()
114 pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); in xics_mask_unknown_vec()
118 xics_ics->mask_unknown(xics_ics, vec); in xics_mask_unknown_vec()
[all …]
/Linux-v6.6/arch/arm64/boot/dts/apple/
Dt6001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6001", "apple,arm-platform";
23 compatible = "simple-bus";
24 #address-cells = <2>;
[all …]
/Linux-v6.6/arch/alpha/kernel/
Dsys_dp264.c1 // SPDX-License-Identifier: GPL-2.0
68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()
71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()
88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()
91 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()
103 cached_irq_mask |= 1UL << d->irq; in dp264_enable_irq()
[all …]
/Linux-v6.6/drivers/iommu/
Dhyperv-iommu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
12 #include <linux/interrupt.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
42 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
46 /* Return error If new irq affinity is out of ioapic_max_cpumask. */ in hyperv_ir_set_affinity()
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
60 .name = "HYPERV-IR",
[all …]

12345678910>>...16