Searched +full:intc +full:- +full:irqpin +full:- +full:r8a7740 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas Interrupt Controller (INTC) for external pins10 - Geert Uytterhoeven <geert+renesas@glider.be>15 - enum:16 - renesas,intc-irqpin-r8a7740 # R-Mobile A117 - renesas,intc-irqpin-r8a7778 # R-Car M1A18 - renesas,intc-irqpin-r8a7779 # R-Car H1[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC8 #include <dt-bindings/clock/r8a7740-clock.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/interrupt-controller/irq.h>13 compatible = "renesas,r8a7740";14 interrupt-parent = <&gic>;15 #address-cells = <1>;16 #size-cells = <1>;19 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Renesas INTC External IRQ Pin Driver34 /* INTC external IRQ PIN hardware register access:36 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)37 * PRIO is read-write 32-bit with 4-bits per IRQ (**)38 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)39 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)40 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)42 * (*) May be accessed by more than one driver instance - lock needed43 * (**) Read-modify-write access by one driver instance - lock needed[all …]
