instruction (full) in projects: Linux-v5.15

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/Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power8/
D	frontend.json	5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct… 11 "BriefDescription": "Branch Instruction Finished", 23 "BriefDescription": "Branch Instruction completed", 71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", 72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch" 89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different … 90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different … 95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No… 96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No… 101 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr… [all …]
D	other.json	305 "BriefDescription": "Completion stall due to VSU scalar instruction", 311 "BriefDescription": "Completion stall due to VSU scalar long latency instruction", 323 "BriefDescription": "Completion stall due to VSU vector instruction", 329 "BriefDescription": "Completion stall due to VSU vector long instruction", 335 "BriefDescription": "Completion stall due to VSU instruction", 359 "BriefDescription": "IFU Finished a (non-branch) instruction", 713 "BriefDescription": "Dispatch/CLB Hold: Sync type instruction", 887 "BriefDescription": "Convert instruction executed", 893 "BriefDescription": "Estimate instruction executed", 899 "BriefDescription": "Round to single precision instruction executed", [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
D	other.json	15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 39 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 42 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power10/
D	frontend.json	5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or… 10 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason." 30 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 35 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power mana… 40 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mappe… 45 …"BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access)… 50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 65 "BriefDescription": "Cycles in which at least one instruction is completed by this thread." 80 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue fu… 85 "BriefDescription": "Marked instruction RC dispatched in L2." [all …]
D	pipeline.json	30 "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss." 45 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a… 60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t… 65 …"BriefDescription": "A branch instruction finished. Includes predicted/mispredicted/unconditional." 70 …"BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish t… 80 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not… 95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl… 100 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 115 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the V… 120 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for… [all …]
D	marked.json	10 …instruction issued. Note that stores always get issued twice, the address gets issued to the LSU a… 15 "BriefDescription": "The thread has dispatched a randomly sampled marked instruction." 20 "BriefDescription": "Marked Branch Taken instruction completed." 25 …"BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. … 30 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 40 "BriefDescription": "Marked Branch instruction finished." 50 …"BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instr… 55 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 70 …"BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. N… 80 …"BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instruc… [all …]
D	cache.json	5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 10 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 15 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 20 …instruction in the pipeline was finishing a load after its data was reloaded from a data source be… 35 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 40 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction… 45 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruct…
D	others.json	35 …instruction. It starts counting when the operation starts to drain to the L2 and it stops counting… 45 "BriefDescription": "Marked Instruction suffered an icache Miss." 55 …ompleted. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1\|2\|4\|8… 80 …"BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions… 85 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 90 …"BriefDescription": "The marked instruction was a decimal floating point operation issued to the V… 95 …"BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measure… 100 …"BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per … 145 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 175 …"BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill… [all …]
/Linux-v5.15/Documentation/virt/kvm/
D	s390-pv.rst	26 the behavior of the SIE instruction. A new format 4 state description 48 of an instruction emulation by KVM, e.g. we can never inject a 63 Instruction emulation 65 With the format 4 state description for PVMs, the SIE instruction already 67 to interpret every instruction, but needs to hand some tasks to KVM; 71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the 73 the instruction data, such as I/O data structures, are filtered. 74 Instruction data is copied to and from the SIDA when needed. Guest 78 Only GR values needed to emulate an instruction will be copied into this 82 the bytes of the instruction text, but with pre-set register values [all …]
/Linux-v5.15/arch/sh/kernel/
D	traps_32.c	79 * handle an instruction that does an unaligned memory access by emulating the 81 * - note that PC _may not_ point to the faulting instruction 82 * (if that instruction is in a branch delay slot) 85 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs regs, in handle_unaligned_ins() argument 93 index = (instruction>>8)&15; / 0x0F00 / in handle_unaligned_ins() 96 index = (instruction>>4)&15; / 0x00F0 */ in handle_unaligned_ins() 99 count = 1<<(instruction&3); in handle_unaligned_ins() 109 switch (instruction>>12) { in handle_unaligned_ins() 111 if (instruction & 8) { in handle_unaligned_ins() 143 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins() [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power9/
D	translation.json	20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)" 55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t… 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request" 80 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on … 100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request" 115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t… [all …]
D	marked.json	5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n… 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 35 …cription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conf… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 75 "BriefDescription": "Vector FP instruction completed" 80 …Description": "The processor's Instruction cache was reloaded from local core's L2 without conflic… 85 …ription": "The processor's Instruction cache was reloaded from a location other than the local cor… 90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi… 115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB" 120 …: "The processor's Instruction cache was reloaded from another chip's memory on the same Node or G… [all …]
D	frontend.json	5 …B with Modified (M) data from another core's L3 on the same chip due to a instruction side request" 15 …aded into the TLB from a location other than the local core's L3 due to a instruction side request" 20 …"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in t… 25 …instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ… 40 … or the original scope was System and it should have been smaller. Counts for an instruction fetch" 45 "BriefDescription": "Marked Instruction RC dispatched in L2" 60 … Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch" 70 …Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. … 75 …s finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an ad… 80 …e. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to c… [all …]
D	cache.json	10 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of… 15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi… 20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p… 35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and… 40 … processor's Instruction cache was reloaded either shared or modified data from another core's L2/… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …n": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Gro… 55 … Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node… 90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor… 100 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod… [all …]
D	metrics.json	8 "BriefDescription": "Count cache branch misprediction per instruction", 44 …"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution p… 50 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and wa… 56 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 68 …"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating P… 134 …"BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to t… 140 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction… 146 …"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response fro… 152 …"BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and… 163 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a … [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/arm64/
D	armv8-common-and-microarch.json	3 …"PublicDescription": "Instruction architecturally executed, Condition code check pass, software in… 6 …"BriefDescription": "Instruction architecturally executed, Condition code check pass, software inc… 9 "PublicDescription": "Level 1 instruction cache refill", 12 "BriefDescription": "Level 1 instruction cache refill" 15 "PublicDescription": "Attributable Level 1 instruction TLB refill", 18 "BriefDescription": "Attributable Level 1 instruction TLB refill" 39 "PublicDescription": "Instruction architecturally executed", 42 "BriefDescription": "Instruction architecturally executed" 51 …"PublicDescription": "Instruction architecturally executed, condition check pass, exception return… 54 … "BriefDescription": "Instruction architecturally executed, condition check pass, exception return" [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwell/
D	frontend.json	3 …instruction decoder queue is empty and can indicate that the application may be bound in the front… 9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 13 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (… 19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 23 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I… 29 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 34 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (… 40 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 44 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I… 50 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellde/
D	frontend.json	5 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 8 …instruction decoder queue is empty and can indicate that the application may be bound in the front… 15 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 18 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (… 25 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 29 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I… 36 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 39 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (… 46 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 50 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellx/
D	frontend.json	5 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 8 …instruction decoder queue is empty and can indicate that the application may be bound in the front… 15 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 18 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (… 25 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 29 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I… 36 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 39 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (… 46 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 50 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I… [all …]
/Linux-v5.15/sound/soc/sof/xtensa/
D	core.c	24 * Instruction Set Architecture (ISA) Reference Manual 27 {0, "IllegalInstructionCause", "Illegal instruction"}, 28 {1, "SyscallCause", "SYSCALL instruction"}, 30 "Processor internal physical address or data error during instruction fetch"}, 36 "MOVSP instruction, if caller’s registers are not in the register file"}, 43 "PIF data error during instruction fetch"}, 47 "PIF address error during instruction fetch"}, 50 {16, "InstTLBMissCause", "Error during Instruction TLB refill"}, 52 "Multiple instruction TLB entries matched"}, 54 "An instruction fetch referenced a virtual address at a ring level less than CRING"}, [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/silvermont/
D	frontend.json	3 …"PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\… 9 "BriefDescription": "Instruction fetches" 12 … "PublicDescription": "This event counts all instruction fetches from the instruction cache.", 18 "BriefDescription": "Instruction fetches from Icache" 21 … counts all instruction fetches that miss the Instruction cache or produce memory requests. This i… 30 …instruction is encountered by the front end of the machine. Other cases include when an instructi… 39 … times a decode restriction reduced the decode throughput due to wrong instruction length predicti… 45 … times a decode restriction reduced the decode throughput due to wrong instruction length predicti…
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen2/
D	cache.json	23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", 82 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-… 166 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modif… 172 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean… 178 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request m… 184 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests … 190 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request m… 196 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request h… 226 …"BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction de… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen3/
D	cache.json	23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", 82 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-… 166 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modif… 172 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-m… 178 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request m… 184 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests … 190 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request m… 196 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request h… 226 …"BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction de… [all …]
/Linux-v5.15/arch/arm/probes/
D	decode.h	39 * Update ITSTATE after normal execution of an IT block instruction. 136 * The following definitions and macros are used to build instruction 161 * instruction. A match is found when (instruction & mask) == value. 164 * Instruction decoding jumps to parsing the new sub-table 'table'. 169 * to complete decoding of the instruction. 172 * The probes instruction handler is set to the value found by 174 * will be used to simulate the instruction when the probe is hit. 178 * The probes instruction handler is set to the value found by 180 * will be used to emulate the instruction when the probe is hit. The 181 * modified instruction (see below) is placed in the probes instruction [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/ivybridge/
D	frontend.json	9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 23 …"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from … 29 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 40 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 44 …"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from … 50 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 61 …ps initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (I… 65 …en uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (I… 71 …en uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (I… [all …]

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