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Searched +full:imx8qxp +full:- +full:usdhc (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8qxp-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
8 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
12 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
16 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
20 compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
24 compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
Dimx8qm-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
12 compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
16 compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
20 compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
30 - items:
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/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: "mmc-controller.yaml"
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
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/Linux-v5.15/drivers/mmc/host/
Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
81 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
138 * open ended multi-blk IO. Otherwise the TC INT wouldn't
148 * The flag tells that the ESDHC controller is an USDHC block that is
160 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
172 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
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