Searched +full:i2c +full:- +full:r1p10 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"7 title: Cadence I2C controller Device Tree Bindings10 - Michal Simek <michal.simek@xilinx.com>13 - $ref: /schemas/i2c/i2c-controller.yaml#18 - cdns,i2c-r1p10 # cadence i2c controller version 1.019 - cdns,i2c-r1p14 # cadence i2c controller version 1.430 clock-frequency:[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "xlnx,zynq-7000";12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";20 clock-latency = <1000>;21 cpu0-supply = <®ulator_vccpint>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * I2C bus driver for the Cadence I2C controller.5 * Copyright (C) 2009 - 2014 Xilinx, Inc.10 #include <linux/i2c.h>18 /* Register offsets for the I2C device. */21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */57 * I2C Address Register Bit mask definitions59 * bits. A write access to this register always initiates a transfer if the I2C62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
