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/Linux-v6.6/tools/perf/pmu-events/arch/x86/knightslanding/
D	cache.json	70 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 111 …refetch code read requests that accounts for responses from snoop request hit with data forwarded… 120 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 129 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 138 …refetch code read requests that accounts for responses from snoop request hit with data forwarded… 147 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 156 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 165 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 174 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 183 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/sandybridge/
D	cache.json	213 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 220 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 234 "BriefDescription": "RFO requests that hit L2 cache.", 255 "BriefDescription": "RFOs that hit cache lines in E state.", 262 "BriefDescription": "RFOs that hit cache lines in M state.", 357 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 366 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 371 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 396 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 424 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/haswell/
D	virtual-memory.json	19 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 27 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 30 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 35 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 38 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 98 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 101 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 106 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 109 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 114 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
D	cache.json	51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 161 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 174 "BriefDescription": "Demand Data Read requests that hit L2 cache", 178 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 192 "BriefDescription": "L2 prefetch requests that hit L2 cache", 195 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 226 "BriefDescription": "RFO requests that hit L2 cache", 229 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 350 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/haswellx/
D	virtual-memory.json	19 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 27 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 30 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 35 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 38 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 98 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 101 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 106 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 109 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 114 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
D	cache.json	51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 161 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 174 "BriefDescription": "Demand Data Read requests that hit L2 cache", 178 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 192 "BriefDescription": "L2 prefetch requests that hit L2 cache", 195 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 226 "BriefDescription": "RFO requests that hit L2 cache", 229 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 350 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/icelake/
D	cache.json	40 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 97 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 142 "BriefDescription": "Demand Data Read requests that hit L2 cache", 145 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 174 "BriefDescription": "RFO requests that hit L2 cache", 177 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 190 "BriefDescription": "SW prefetch requests that hit L2 cache.", 193 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 322 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 327 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/rocketlake/
D	cache.json	40 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 97 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 142 "BriefDescription": "Demand Data Read requests that hit L2 cache", 145 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 174 "BriefDescription": "RFO requests that hit L2 cache", 177 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 190 "BriefDescription": "SW prefetch requests that hit L2 cache.", 193 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 322 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 327 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	54 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 69 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 74 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 89 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 94 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 109 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 114 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 196 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", 201 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF… 216 …"Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/ivytown/
D	cache.json	184 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 197 "BriefDescription": "Demand Data Read requests that hit L2 cache", 200 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 205 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 208 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 221 "BriefDescription": "RFO requests that hit L2 cache", 224 "PublicDescription": "RFO requests that hit L2 cache.", 245 "BriefDescription": "RFOs that hit cache lines in M state", 248 "PublicDescription": "RFOs that hit cache lines in M state.", 365 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/jaketown/
D	cache.json	213 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 220 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 234 "BriefDescription": "RFO requests that hit L2 cache.", 255 "BriefDescription": "RFOs that hit cache lines in E state.", 262 "BriefDescription": "RFOs that hit cache lines in M state.", 356 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 364 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 369 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 397 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 424 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	54 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 69 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 74 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 89 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 94 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 109 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 114 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 206 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", 211 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE… 216 …on": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other proces… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/amdzen3/
D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …cheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …eable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line… 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
D	branch.json	`27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", 33 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 39 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 45 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit …`
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/ampere/emag/
D	cache.json	132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" 144 "PublicDescription": "Page walk cache level-2 stage-1 hit", 147 "BriefDescription": "Page walk, L2 stage-1 hit" 150 "PublicDescription": "Page walk cache level-1 stage-2 hit", 153 "BriefDescription": "Page walk, L1 stage-2 hit" 156 "PublicDescription": "Page walk cache level-2 stage-2 hit", 159 "BriefDescription": "Page walk, L2 stage-2 hit"
/Linux-v6.6/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 34 "EventName": "L2_REQUEST.HIT", 35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 72 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 75 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRA… 80 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 83 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 88 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 91 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 96 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/snowridgex/
D	cache.json	32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 34 "EventName": "L2_REQUEST.HIT", 35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 72 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 75 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRA… 80 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 83 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 88 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 91 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 96 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/skylakex/
D	cache.json	22 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 94 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 147 "BriefDescription": "Demand Data Read requests that hit L2 cache", 150 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 171 …": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", 174 …ts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", 195 "BriefDescription": "RFO requests that hit L2 cache", 198 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 336 …"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop… 403 …on": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	cache.json	55 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 103 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl… 127 …ounts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. T… 179 "BriefDescription": "Demand Data Read requests that hit L2 cache", 182 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 213 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl… 218 "BriefDescription": "RFO requests that hit L2 cache", 221 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 234 "BriefDescription": "SW prefetch requests that hit L2 cache.", 237 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/s390/cf_z16/
D	extended.json	111 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", 112 …rced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 118 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", 119 … from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." 139 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit", 140 … sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 146 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit", 147 …as sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 209 …n": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit", 210 …e line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
D	core-imp-def.json	15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB", 18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB" 21 …"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of … 24 …"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of B… 27 …"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB th… 30 …"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB tha… 33 …"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB th… 36 …"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB tha… 39 …tion": "Predictable unconditional branch speculatively executed that did not hit any level of BTB", 42 …ption": "Predictable unconditional branch speculatively executed that did not hit any level of BTB" [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/alderlaken/
D	cache.json	19 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 22 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRA… 27 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 30 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 35 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 38 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 43 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… 46 …e to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level C… 51 …s the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRA… 58 …s the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (No… [all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/icelakex/
D	cache.json	40 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 89 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 126 "BriefDescription": "Demand Data Read requests that hit L2 cache", 129 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 142 "BriefDescription": "RFO requests that hit L2 cache", 145 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 158 "BriefDescription": "SW prefetch requests that hit L2 cache.", 161 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 308 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 313 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/Linux-v6.6/Documentation/admin-guide/device-mapper/
D	cache-policies.rst	12 The policy can return a simple HIT or MISS or issue a migration. 21 doesn't update states (eg, hit counts) for a block more than once 67 pointers. It avoids storing an explicit hit count for each block. It 79 based on their hit count (~ln(hit count)). This meant the bottom 84 smq does not maintain a hit count, instead it swaps hit entries with 91 The mq policy maintained a hit count for each cache block. For a 92 different block to get promoted to the cache its hit count has to 96 smq doesn't maintain hit counts, so a lot of this problem just goes
/Linux-v6.6/tools/perf/pmu-events/arch/x86/meteorlake/
D	cache.json	52 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 98 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl… 104 "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", 106 "EventName": "L2_REQUEST.HIT", 107 …"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]… 134 …ounts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. T… 193 "BriefDescription": "Demand Data Read requests that hit L2 cache", 196 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 211 … "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", 213 "EventName": "L2_RQSTS.HIT", [all …]

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