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/Linux-v6.1/tools/perf/pmu-events/arch/x86/knightslanding/
D	cache.json	79 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 126 …prefetch code read requests that accounts for reponses from snoop request hit with data forwarded… 137 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 148 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 159 …prefetch code read requests that accounts for reponses from snoop request hit with data forwarded… 170 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 181 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 192 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 203 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 214 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	68 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 85 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 92 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 109 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 116 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 133 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 140 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 238 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", 246 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF… 264 …"Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/
D	cache.json	271 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 280 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 298 "BriefDescription": "RFO requests that hit L2 cache.", 325 "BriefDescription": "RFOs that hit cache lines in E state.", 334 "BriefDescription": "RFOs that hit cache lines in M state.", 457 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 468 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 473 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 504 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 540 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen3/
D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …cheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …eable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line… 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
D	branch.json	`27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", 33 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 39 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 45 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit …`
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/ampere/emag/
D	cache.json	132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" 144 "PublicDescription": "Page walk cache level-2 stage-1 hit", 147 "BriefDescription": "Page walk, L2 stage-1 hit" 150 "PublicDescription": "Page walk cache level-1 stage-2 hit", 153 "BriefDescription": "Page walk, L1 stage-2 hit" 156 "PublicDescription": "Page walk cache level-2 stage-2 hit", 159 "BriefDescription": "Page walk, L2 stage-2 hit"
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/
D	virtual-memory.json	23 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 38 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 48 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 122 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 127 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 132 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 137 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 142 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
D	cache.json	63 "BriefDescription": "Not rejected writebacks that hit L2 cache", 68 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 216 "BriefDescription": "Demand Data Read requests that hit L2 cache", 222 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 238 "BriefDescription": "L2 prefetch requests that hit L2 cache", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 280 "BriefDescription": "RFO requests that hit L2 cache", 285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 434 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/
D	virtual-memory.json	23 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 38 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 48 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 122 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 127 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 132 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 137 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 142 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/
D	cache.json	59 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 144 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 210 "BriefDescription": "Demand Data Read requests that hit L2 cache", 216 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 234 "BriefDescription": "RFO requests that hit L2 cache", 240 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 258 "BriefDescription": "SW prefetch requests that hit L2 cache.", 264 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 440 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 448 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z16/
D	extended.json	111 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", 112 …ced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 118 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", 119 …from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." 139 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit", 140 … sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 146 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit", 147 …as sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 209 …n": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit", 210 …e line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/snowridgex/
D	cache.json	48 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 52 "EventName": "L2_REQUEST.HIT", 55 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 108 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 118 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 125 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 130 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 137 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 142 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… 149 …e to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level C… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	48 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 52 "EventName": "L2_REQUEST.HIT", 55 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 108 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 118 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 125 …e to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (no… 130 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 137 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 142 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… 149 …e to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level C… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	81 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 99 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 107 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 125 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 133 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 151 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 159 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 281 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", 291 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE… 296 …on": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other proces… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivytown/
D	cache.json	230 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 245 "BriefDescription": "Demand Data Read requests that hit L2 cache", 250 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 255 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 260 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 275 "BriefDescription": "RFO requests that hit L2 cache", 280 "PublicDescription": "RFO requests that hit L2 cache.", 305 "BriefDescription": "RFOs that hit cache lines in M state", 310 "PublicDescription": "RFOs that hit cache lines in M state.", 455 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… [all …]
/Linux-v6.1/Documentation/admin-guide/device-mapper/
D	cache-policies.rst	12 The policy can return a simple HIT or MISS or issue a migration. 21 doesn't update states (eg, hit counts) for a block more than once 67 pointers. It avoids storing an explicit hit count for each block. It 79 based on their hit count (~ln(hit count)). This meant the bottom 84 smq does not maintain a hit count, instead it swaps hit entries with 91 The mq policy maintained a hit count for each cache block. For a 92 different block to get promoted to the cache its hit count has to 96 smq doesn't maintain hit counts, so a lot of this problem just goes
/Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	cache.json	81 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 153 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl… 189 …ounts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. T… 266 "BriefDescription": "Demand Data Read requests that hit L2 cache", 272 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 319 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl… 325 "BriefDescription": "RFO requests that hit L2 cache", 331 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 349 "BriefDescription": "SW prefetch requests that hit L2 cache.", 355 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/
D	cache.json	271 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 280 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 298 "BriefDescription": "RFO requests that hit L2 cache.", 325 "BriefDescription": "RFOs that hit cache lines in E state.", 334 "BriefDescription": "RFOs that hit cache lines in M state.", 456 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 466 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 471 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 507 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 542 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/
D	cache.json	28 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 118 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 183 "BriefDescription": "Demand Data Read requests that hit L2 cache", 188 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 213 …": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", 218 …ts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", 243 "BriefDescription": "RFO requests that hit L2 cache", 248 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 416 …"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop… 497 …on": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen1/
D	cache.json	25 …"BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 … 35 …"BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the… 111 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 206 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 212 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.", 218 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L… 224 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 236 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 242 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", 266 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … [all …]
/Linux-v6.1/tools/perf/util/
D	stream.c	68 * The cnodes with high hit number are hot callchains. 74 u64 hit; in evsel_streams__set_hot_cnode() local 85 * way to find the cnode with smallest hit number and replace. in evsel_streams__set_hot_cnode() 87 hit = (es->streams[0].cnode)->hit; in evsel_streams__set_hot_cnode() 89 if ((es->streams[i].cnode)->hit < hit) { in evsel_streams__set_hot_cnode() 90 hit = (es->streams[i].cnode)->hit; in evsel_streams__set_hot_cnode() 95 if (cnode->hit > hit) in evsel_streams__set_hot_cnode() 234 pct = (double)base_cnode->hit / (double)es_base->streams_hits; in print_callchain_pair() 238 pct = (double)pair_cnode->hit / (double)es_pair->streams_hits; in print_callchain_pair() 277 pct = (double)cnode->hit / (double)es->streams_hits; in print_stream_callchain()
/Linux-v6.1/fs/exfat/
D	cache.c	89 struct exfat_cache hit = &nohit, p; in exfat_cache_lookup() local 95 if (p->fcluster <= fclus && hit->fcluster < p->fcluster) { in exfat_cache_lookup() 96 hit = p; in exfat_cache_lookup() 97 if (hit->fcluster + hit->nr_contig < fclus) { in exfat_cache_lookup() 98 offset = hit->nr_contig; in exfat_cache_lookup() 100 offset = fclus - hit->fcluster; in exfat_cache_lookup() 105 if (hit != &nohit) { in exfat_cache_lookup() 106 exfat_cache_update_lru(inode, hit); in exfat_cache_lookup() 109 cid->nr_contig = hit->nr_contig; in exfat_cache_lookup() 110 cid->fcluster = hit->fcluster; in exfat_cache_lookup() [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen2/
D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
/Linux-v6.1/kernel/trace/
D	ring_buffer_benchmark.c	237 unsigned long hit = 0; in ring_buffer_producer() local 258 hit++; in ring_buffer_producer() 335 trace_printk("Hit: %ld\n", hit); in ring_buffer_producer() 340 hit /= (long)time; in ring_buffer_producer() 344 trace_printk("Entries per millisec: %ld\n", hit); in ring_buffer_producer() 346 if (hit) { in ring_buffer_producer() 348 avg = NSEC_PER_MSEC / hit; in ring_buffer_producer() 357 hit + missed); in ring_buffer_producer() 359 /* it is possible that hit + missed will overflow and be zero */ in ring_buffer_producer() 360 if (!(hit + missed)) { in ring_buffer_producer() [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/
D	cache.json	59 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 132 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 186 "BriefDescription": "Demand Data Read requests that hit L2 cache", 192 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 210 "BriefDescription": "RFO requests that hit L2 cache", 216 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 234 "BriefDescription": "SW prefetch requests that hit L2 cache.", 240 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 439 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 447 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]

12 3 4 5 6 7 8 9 10 >>...52