hit (full) in projects: Linux-v5.15 - OpenGrok search results

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/Linux-v5.15/tools/perf/pmu-events/arch/x86/knightslanding/
D	cache.json	59 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 135 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 146 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 157 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 168 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 201 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 212 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 223 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 234 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 267 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	158 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 164 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 170 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 176 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 218 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 224 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 230 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 254 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… 262 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… 267 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/haswell/
D	cache.json	66 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 73 "BriefDescription": "Demand Data Read requests that hit L2 cache", 77 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 83 "BriefDescription": "RFO requests that hit L2 cache", 87 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 97 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 103 "BriefDescription": "L2 prefetch requests that hit L2 cache", 170 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 176 "BriefDescription": "Not rejected writebacks that hit L2 cache", 588 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
D	virtual-memory.json	62 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 68 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 72 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 78 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 88 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 161 … counts store operations from a 4K page that miss the first DTLB level but hit the second and do n… 167 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 171 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 177 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 181 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/haswellx/
D	cache.json	68 "BriefDescription": "Demand Data Read requests that hit L2 cache", 72 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 79 "BriefDescription": "RFO requests that hit L2 cache", 82 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 92 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 99 "BriefDescription": "L2 prefetch requests that hit L2 cache", 102 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 172 "BriefDescription": "Not rejected writebacks that hit L2 cache", 175 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 582 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
D	virtual-memory.json	64 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 67 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 74 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 77 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 84 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 163 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 166 … counts store operations from a 4K page that miss the first DTLB level but hit the second and do n… 173 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 176 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 183 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/sandybridge/
D	cache.json	8 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 26 "BriefDescription": "RFO requests that hit L2 cache.", 80 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 116 "BriefDescription": "RFOs that hit cache lines in E state.", 125 "BriefDescription": "RFOs that hit cache lines in M state.", 504 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… 520 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 530 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 535 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 546 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/arm64/ampere/emag/
D	cache.json	132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" 144 "PublicDescription": "Page walk cache level-2 stage-1 hit", 147 "BriefDescription": "Page walk, L2 stage-1 hit" 150 "PublicDescription": "Page walk cache level-1 stage-2 hit", 153 "BriefDescription": "Page walk, L1 stage-2 hit" 156 "PublicDescription": "Page walk cache level-2 stage-2 hit", 159 "BriefDescription": "Page walk, L2 stage-2 hit"
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen3/
D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …cheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …eable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line… 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
D	branch.json	`27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", 33 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 39 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 45 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit …`
/Linux-v5.15/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	39 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 46 …to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (no… 51 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 58 …e to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", 63 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… 70 …to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level C… 75 …s the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (No… 86 … "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 93 …": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", 98 …Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other… [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellx/
D	cache.json	61 "BriefDescription": "Demand Data Read requests that hit L2 cache", 64 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", 71 "BriefDescription": "RFO requests that hit L2 cache.", 89 "BriefDescription": "L2 prefetch requests that hit L2 cache", 92 … event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefet… 102 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 157 "BriefDescription": "Not rejected writebacks that hit L2 cache", 160 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 190 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 561 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	179 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 186 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 192 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 199 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 244 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 251 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 257 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 284 …"PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Req… 294 … "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.", 314 …nd cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other proces… [all …]
/Linux-v5.15/Documentation/admin-guide/device-mapper/
D	cache-policies.rst	12 The policy can return a simple HIT or MISS or issue a migration. 21 doesn't update states (eg, hit counts) for a block more than once 67 pointers. It avoids storing an explicit hit count for each block. It 79 based on their hit count (~ln(hit count)). This meant the bottom 84 smq does not maintain a hit count, instead it swaps hit entries with 91 The mq policy maintained a hit count for each cache block. For a 92 different block to get promoted to the cache its hit count has to 96 smq doesn't maintain hit counts, so a lot of this problem just goes
/Linux-v5.15/tools/perf/pmu-events/arch/x86/ivytown/
D	cache.json	3 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 9 "BriefDescription": "Demand Data Read requests that hit L2 cache", 23 "PublicDescription": "RFO requests that hit L2 cache.", 29 "BriefDescription": "RFO requests that hit L2 cache", 53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 123 "PublicDescription": "RFOs that hit cache lines in M state.", 129 "BriefDescription": "RFOs that hit cache lines in M state", 546 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/jaketown/
D	cache.json	97 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… 122 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 131 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 135 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 145 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 344 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 353 "BriefDescription": "RFO requests that hit L2 cache.", 389 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 416 "BriefDescription": "RFOs that hit cache lines in E state.", 425 "BriefDescription": "RFOs that hit cache lines in M state.", [all …]
/Linux-v5.15/tools/perf/util/
D	stream.c	68 * The cnodes with high hit number are hot callchains. 74 u64 hit; in evsel_streams__set_hot_cnode() local 85 * way to find the cnode with smallest hit number and replace. in evsel_streams__set_hot_cnode() 87 hit = (es->streams[0].cnode)->hit; in evsel_streams__set_hot_cnode() 89 if ((es->streams[i].cnode)->hit < hit) { in evsel_streams__set_hot_cnode() 90 hit = (es->streams[i].cnode)->hit; in evsel_streams__set_hot_cnode() 95 if (cnode->hit > hit) in evsel_streams__set_hot_cnode() 234 pct = (double)base_cnode->hit / (double)es_base->streams_hits; in print_callchain_pair() 238 pct = (double)pair_cnode->hit / (double)es_pair->streams_hits; in print_callchain_pair() 277 pct = (double)cnode->hit / (double)es->streams_hits; in print_stream_callchain()
D	mem-events.h	`64 u32 st_l1hit; /* count of stores that hit L1D / 68 u32 ld_shared; / shared loads, rmt/lcl DRAM - snp hit / 74 u32 ld_l1hit; / count of loads that hit L1D / 75 u32 ld_l2hit; / count of loads that hit L2D / 76 u32 ld_llchit; / count of loads that hit LLC / 80 u32 rmt_hit; / count of loads with remote hit clean; */`
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen1/
D	cache.json	25 …"BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 … 35 …"BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the… 111 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 206 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 212 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.", 218 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L… 224 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 236 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 242 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", 266 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … [all …]
/Linux-v5.15/fs/exfat/
D	cache.c	89 struct exfat_cache hit = &nohit, p; in exfat_cache_lookup() local 95 if (p->fcluster <= fclus && hit->fcluster < p->fcluster) { in exfat_cache_lookup() 96 hit = p; in exfat_cache_lookup() 97 if (hit->fcluster + hit->nr_contig < fclus) { in exfat_cache_lookup() 98 offset = hit->nr_contig; in exfat_cache_lookup() 100 offset = fclus - hit->fcluster; in exfat_cache_lookup() 105 if (hit != &nohit) { in exfat_cache_lookup() 106 exfat_cache_update_lru(inode, hit); in exfat_cache_lookup() 109 cid->nr_contig = hit->nr_contig; in exfat_cache_lookup() 110 cid->fcluster = hit->fcluster; in exfat_cache_lookup() [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/icelake/
D	other.json	3 …"Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the … 63 …re prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit… 90 … requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the … 120 …ta cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the … 165 …"Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the … 180 … requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the … 207 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach… 267 …"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in … 297 …"Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the … 327 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach… [all …]
/Linux-v5.15/kernel/trace/
D	ring_buffer_benchmark.c	237 unsigned long hit = 0; in ring_buffer_producer() local 258 hit++; in ring_buffer_producer() 335 trace_printk("Hit: %ld\n", hit); in ring_buffer_producer() 340 hit /= (long)time; in ring_buffer_producer() 344 trace_printk("Entries per millisec: %ld\n", hit); in ring_buffer_producer() 346 if (hit) { in ring_buffer_producer() 348 avg = NSEC_PER_MSEC / hit; in ring_buffer_producer() 357 hit + missed); in ring_buffer_producer() 359 /* it is possible that hit + missed will overflow and be zero */ in ring_buffer_producer() 360 if (!(hit + missed)) { in ring_buffer_producer() [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen2/
D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/
D	cache.json	28 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 118 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 183 "BriefDescription": "Demand Data Read requests that hit L2 cache", 188 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 213 …": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", 218 …ts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", 243 "BriefDescription": "RFO requests that hit L2 cache", 248 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 401 …"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop… 482 …on": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding… [all …]
/Linux-v5.15/fs/fat/
D	cache.c	86 struct fat_cache hit = &nohit, p; in fat_cache_lookup() local 92 if (p->fcluster <= fclus && hit->fcluster < p->fcluster) { in fat_cache_lookup() 93 hit = p; in fat_cache_lookup() 94 if ((hit->fcluster + hit->nr_contig) < fclus) { in fat_cache_lookup() 95 offset = hit->nr_contig; in fat_cache_lookup() 97 offset = fclus - hit->fcluster; in fat_cache_lookup() 102 if (hit != &nohit) { in fat_cache_lookup() 103 fat_cache_update_lru(inode, hit); in fat_cache_lookup() 106 cid->nr_contig = hit->nr_contig; in fat_cache_lookup() 107 cid->fcluster = hit->fcluster; in fat_cache_lookup() [all …]

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Project(s)	No entries found Linux Linux-v4.19 Linux-v5.10 Linux-v5.15 Linux-v5.4 Linux-v6.1 Linux-v6.6

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