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/Linux-v5.4/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c35 { .name = "etnaviv-gpu,2d" },
43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
49 *value = gpu->identity.model; in etnaviv_gpu_get_param()
53 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
57 *value = gpu->identity.features; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
[all …]
Detnaviv_buffer.c88 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
93 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
101 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
103 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
114 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
120 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
122 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump()
131 * The GPU may be executing this WAIT while we're modifying it, so we have
132 * to write it in a specific order to avoid the GPU branching to somewhere
150 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
[all …]
Detnaviv_drv.c37 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
44 priv->gpu[i] = NULL; in load_gpu()
67 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
70 if (gpu) { in etnaviv_open()
71 rq = &gpu->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; in etnaviv_open()
93 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
95 if (gpu) in etnaviv_postclose()
129 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
134 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
137 * Lock the GPU to avoid a MMU context switch just now and elevate in etnaviv_mmu_show()
[all …]
Detnaviv_sched.c80 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
88 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
93 * If the GPU managed to complete this jobs fence, the timout is in etnaviv_sched_timedout_job()
100 * If the GPU is still making forward progress on the front-end (which in etnaviv_sched_timedout_job()
104 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
105 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
107 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job()
112 drm_sched_stop(&gpu->sched, sched_job); in etnaviv_sched_timedout_job()
117 /* get the GPU back into the init state */ in etnaviv_sched_timedout_job()
119 etnaviv_gpu_recover_hang(gpu); in etnaviv_sched_timedout_job()
[all …]
Detnaviv_gpu.h85 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
150 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
152 writel(data, gpu->mmio + reg); in gpu_write()
155 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
157 return readl(gpu->mmio + reg); in gpu_read()
160 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
162 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
163 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
166 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
169 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
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Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
178 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
180 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
182 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
185 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
192 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
195 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
197 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
[all …]
Detnaviv_perfmon.c18 u32 (*sample)(struct etnaviv_gpu *gpu,
39 static u32 perf_reg_read(struct etnaviv_gpu *gpu, in perf_reg_read() argument
43 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
45 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
48 static u32 pipe_reg_read(struct etnaviv_gpu *gpu, in pipe_reg_read() argument
52 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
56 for (i = 0; i < gpu->identity.pixel_pipes; i++) { in pipe_reg_read()
59 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read()
60 gpu_write(gpu, domain->profile_config, signal->data); in pipe_reg_read()
61 value += gpu_read(gpu, domain->profile_read); in pipe_reg_read()
[all …]
/Linux-v5.4/drivers/gpu/drm/msm/
Dmsm_gpu.c27 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_target() local
35 if (gpu->funcs->gpu_set_freq) in msm_devfreq_target()
36 gpu->funcs->gpu_set_freq(gpu, (u64)*freq); in msm_devfreq_target()
38 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
48 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_dev_status() local
51 if (gpu->funcs->gpu_get_freq) in msm_devfreq_get_dev_status()
52 status->current_frequency = gpu->funcs->gpu_get_freq(gpu); in msm_devfreq_get_dev_status()
54 status->current_frequency = clk_get_rate(gpu->core_clk); in msm_devfreq_get_dev_status()
56 status->busy_time = gpu->funcs->gpu_busy(gpu); in msm_devfreq_get_dev_status()
59 status->total_time = ktime_us_delta(time, gpu->devfreq.time); in msm_devfreq_get_dev_status()
[all …]
Dmsm_gpu.h44 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
45 int (*hw_init)(struct msm_gpu *gpu);
46 int (*pm_suspend)(struct msm_gpu *gpu);
47 int (*pm_resume)(struct msm_gpu *gpu);
48 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
56 /* show GPU status in debugfs: */
[all …]
Dmsm_debugfs.c29 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local
36 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
37 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
49 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local
56 gpu->funcs->gpu_state_put(show_priv->state); in msm_gpu_release()
68 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open() local
72 if (!gpu || !gpu->funcs->gpu_state_get) in msm_gpu_open()
83 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_open()
84 show_priv->state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_open()
85 pm_runtime_put_sync(&gpu->pdev->dev); in msm_gpu_open()
[all …]
/Linux-v5.4/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.c15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
36 if (!adreno_idle(gpu, ring)) in a6xx_idle()
39 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
40 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", in a6xx_idle()
41 gpu->name, __builtin_return_address(0), in a6xx_idle()
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
[all …]
Da5xx_gpu.c17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_flush() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
43 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
46 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit, in a5xx_submit_in_rb() argument
49 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb()
94 a5xx_flush(gpu, ring); in a5xx_submit_in_rb()
95 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb()
101 a5xx_idle(gpu, ring); in a5xx_submit_in_rb()
103 msm_gpu_retire(gpu); in a5xx_submit_in_rb()
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Da3xx_gpu.c32 static void a3xx_dump(struct msm_gpu *gpu);
33 static bool a3xx_idle(struct msm_gpu *gpu);
35 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
37 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
58 gpu->funcs->flush(gpu, ring); in a3xx_me_init()
59 return a3xx_idle(gpu); in a3xx_me_init()
62 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
64 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_hw_init()
69 DBG("%s", gpu->name); in a3xx_hw_init()
73 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
[all …]
Da4xx_gpu.c25 static void a4xx_dump(struct msm_gpu *gpu);
26 static bool a4xx_idle(struct msm_gpu *gpu);
32 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
34 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
37 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
39 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
41 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
43 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
45 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
47 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
[all …]
Da5xx_power.c103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
133 /* Hard code the A530 GPU thermal sensor ID for the GPMU */ in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
[all …]
Dadreno_gpu.h68 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
98 * of gpu firmware to linux-firmware, the fw files were
122 * GPU specific offsets will be exported by GPU specific
148 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) in adreno_is_a2xx() argument
150 return (gpu->revn < 300); in adreno_is_a2xx()
153 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) in adreno_is_a20x() argument
155 return (gpu->revn < 210); in adreno_is_a20x()
158 static inline bool adreno_is_a225(struct adreno_gpu *gpu) in adreno_is_a225() argument
160 return gpu->revn == 225; in adreno_is_a225()
163 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) in adreno_is_a3xx() argument
[all …]
Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
15 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
56 gpu->funcs->flush(gpu, ring); in a2xx_me_init()
57 return a2xx_idle(gpu); in a2xx_me_init()
60 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument
62 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a2xx_hw_init()
67 msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error); in a2xx_hw_init()
69 DBG("%s", gpu->name); in a2xx_hw_init()
[all …]
Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
79 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
86 DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name); in a5xx_preempt_timer()
[all …]
Da5xx_debugfs.c14 static int pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument
21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
29 static int me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument
36 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
38 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
44 static int meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument
49 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
53 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
59 static int roq_print(struct msm_gpu *gpu, struct drm_printer *p) in roq_print() argument
[all …]
Dadreno_gpu.c23 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
26 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
61 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
97 if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { in zap_shader_load_mdt()
133 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
135 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
136 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
148 /* Each GPU has a target specific zap shader firmware name to use */ in adreno_zap_shader_load()
156 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
159 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) in adreno_get_param() argument
[all …]
Da6xx_gpu_state.c112 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
115 dumper->ptr = msm_gem_kernel_new_locked(gpu->dev, in a6xx_crashdumper_init()
116 SZ_1M, MSM_BO_UNCACHED, gpu->aspace, in a6xx_crashdumper_init()
125 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
128 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
142 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO, in a6xx_crashdumper_run()
145 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
147 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
150 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
156 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument
[all …]
/Linux-v5.4/Documentation/gpu/
Di915.rst19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
[all …]
Ddrm-kms-helpers.rst53 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
59 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
68 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
74 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c
83 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c
89 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
95 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
101 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
107 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
113 .. kernel-doc:: drivers/gpu/drm/drm_format_helper.c
[all …]
Damdgpu.rst13 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
31 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
34 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
40 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
43 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
49 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
52 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
58 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
61 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
67 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
[all …]
/Linux-v5.4/drivers/gpu/drm/
DKconfig164 GPU memory management subsystem for devices with multiple
165 GPU memory types. Will be enabled automatically if a device driver
202 source "drivers/gpu/drm/i2c/Kconfig"
204 source "drivers/gpu/drm/arm/Kconfig"
223 source "drivers/gpu/drm/radeon/Kconfig"
226 tristate "AMD GPU"
242 source "drivers/gpu/drm/amd/amdgpu/Kconfig"
244 source "drivers/gpu/drm/nouveau/Kconfig"
246 source "drivers/gpu/drm/i915/Kconfig"
263 running GPU in a headless machines. Choose this option to get
[all …]

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