| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
66 clock-names = "xo", "gpll0";
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| D | qcom,mmcc.yaml | 138 - const: gpll0
168 - const: gpll0
199 - const: gpll0
235 - const: gpll0
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| D | qcom,gpucc-sm8350.yaml | 27 - description: GPLL0 main branch source
28 - description: GPLL0 div branch source
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| D | qcom,gpucc-sdm660.yaml | 27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
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| D | qcom,qcm2290-dispcc.yaml | 26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
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| D | qcom,gpucc.yaml | 40 - description: GPLL0 main branch source
41 - description: GPLL0 div branch source
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| D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
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| D | qcom,sm6115-dispcc.yaml | 30 - description: GPLL0 DISP DIV clock from GCC
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| D | qcom,sc7180-dispcc.yaml | 25 - description: GPLL0 source from GCC
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| /Linux-v6.1/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 55 #define GPLL0 165
62 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | gcc-sc7180.c | 36 static struct clk_alpha_pll gpll0 = { variable
43 .name = "gpll0",
69 &gpll0.clkr.hw,
82 &gpll0.clkr.hw,
170 { .hw = &gpll0.clkr.hw },
177 { .hw = &gpll0.clkr.hw },
192 { .hw = &gpll0.clkr.hw },
209 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sm6350.c | 34 static struct clk_alpha_pll gpll0 = { variable
41 .name = "gpll0",
66 &gpll0.clkr.hw,
88 &gpll0.clkr.hw,
104 &gpll0.clkr.hw,
127 &gpll0.clkr.hw,
143 &gpll0.clkr.hw,
160 { .hw = &gpll0.clkr.hw },
193 { .hw = &gpll0.clkr.hw },
252 &gpll0.clkr.hw,
[all …]
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| D | gcc-qcm2290.c | 57 static struct clk_alpha_pll gpll0 = { variable
64 .name = "gpll0",
88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
416 { .hw = &gpll0.clkr.hw },
429 { .hw = &gpll0.clkr.hw },
443 { .hw = &gpll0.clkr.hw },
459 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
494 { .hw = &gpll0.clkr.hw },
512 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sm6115.c | 56 static struct clk_alpha_pll gpll0 = { variable
65 .name = "gpll0",
89 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
109 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
466 { .hw = &gpll0.clkr.hw },
479 { .hw = &gpll0.clkr.hw },
493 { .hw = &gpll0.clkr.hw },
508 { .hw = &gpll0.clkr.hw },
523 { .hw = &gpll0.clkr.hw },
539 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sm6375.c | 60 static struct clk_alpha_pll gpll0 = { variable
67 .name = "gpll0",
92 &gpll0.clkr.hw,
114 &gpll0.clkr.hw,
446 { .hw = &gpll0.clkr.hw },
459 { .hw = &gpll0.clkr.hw },
473 { .hw = &gpll0.clkr.hw },
480 { .hw = &gpll0.clkr.hw },
496 { .hw = &gpll0.clkr.hw },
514 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sdx55.c | 37 static struct clk_alpha_pll gpll0 = { variable
46 .name = "gpll0",
74 &gpll0.clkr.hw,
145 { .hw = &gpll0.clkr.hw },
152 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
185 { .hw = &gpll0.clkr.hw },
213 { .hw = &gpll0.clkr.hw },
1568 [GPLL0] = &gpll0.clkr,
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| D | gcc-mdm9607.c | 55 static struct clk_alpha_pll_postdiv gpll0 = { variable
60 .name = "gpll0",
74 { .hw = &gpll0.clkr.hw },
115 { .hw = &gpll0.clkr.hw },
158 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0.clkr.hw },
233 { .hw = &gpll0.clkr.hw },
1478 [GPLL0] = &gpll0.clkr,
1605 /* Vote for GPLL0 to turn on. Needed by acpuclock. */ in gcc_mdm9607_probe()
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| D | mmcc-msm8996.c | 54 { .fw_name = "gpll0", .name = "gpll0" },
356 { .fw_name = "gpll0", .name = "gpll0" },
382 { .fw_name = "gpll0", .name = "gpll0" },
398 { .fw_name = "gpll0", .name = "gpll0" },
414 { .fw_name = "gpll0", .name = "gpll0" },
430 { .fw_name = "gpll0", .name = "gpll0" },
446 { .fw_name = "gpll0", .name = "gpll0" },
465 { .fw_name = "gpll0", .name = "gpll0" },
484 { .fw_name = "gpll0", .name = "gpll0" },
504 { .fw_name = "gpll0", .name = "gpll0" },
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| D | gcc-msm8953.c | 70 static struct clk_alpha_pll_postdiv gpll0 = { variable
74 .name = "gpll0",
244 { .hw = &gpll0.clkr.hw },
256 { .hw = &gpll0.clkr.hw },
679 { .hw = &gpll0.clkr.hw },
749 { .hw = &gpll0.clkr.hw },
784 { .hw = &gpll0.clkr.hw },
850 { .hw = &gpll0.clkr.hw },
913 { .hw = &gpll0.clkr.hw },
1020 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sdm845.c | 38 static struct clk_alpha_pll gpll0 = { variable
45 .name = "gpll0",
107 &gpll0.clkr.hw,
122 { .hw = &gpll0.clkr.hw },
135 { .hw = &gpll0.clkr.hw },
157 { .hw = &gpll0.clkr.hw },
177 { .hw = &gpll0.clkr.hw },
184 { .hw = &gpll0.clkr.hw },
191 { .hw = &gpll0.clkr.hw },
197 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sdx65.c | 35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
66 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
80 { .hw = &gpll0.clkr.hw },
86 { .hw = &gpll0.clkr.hw },
99 { .hw = &gpll0.clkr.hw },
1512 [GPLL0] = &gpll0.clkr,
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| D | gcc-sdm660.c | 83 static struct clk_alpha_pll_postdiv gpll0 = { variable
87 .name = "gpll0",
178 { .hw = &gpll0.clkr.hw },
189 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll0.clkr.hw },
237 { .hw = &gpll0.clkr.hw },
253 { .hw = &gpll0.clkr.hw },
267 { .hw = &gpll0.clkr.hw },
1606 &gpll0.clkr.hw,
1672 &gpll0.clkr.hw,
[all …]
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| D | gcc-ipq6018.c | 82 static struct clk_alpha_pll_postdiv gpll0 = { variable
87 .name = "gpll0",
98 { .hw = &gpll0.clkr.hw},
294 { .hw = &gpll0.clkr.hw },
373 { .hw = &gpll0.clkr.hw },
426 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
632 { .hw = &gpll0.clkr.hw },
666 { .hw = &gpll0.clkr.hw },
911 { .hw = &gpll0.clkr.hw },
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 49 - description: GPLL0 Clock
196 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | qcom,gcc-mdm9607.h | 9 #define GPLL0 0 macro
|
