| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
66 clock-names = "xo", "gpll0";
|
| D | qcom,gpucc-sdm660.yaml | 27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
|
| D | qcom,gpucc.yaml | 36 - description: GPLL0 main branch source
37 - description: GPLL0 div branch source
|
| D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
|
| D | qcom,sc7180-dispcc.yaml | 25 - description: GPLL0 source from GCC
|
| D | qcom,sc7280-dispcc.yaml | 25 - description: GPLL0 source from GCC
|
| D | qcom,mmcc.yaml | 49 - const: gpll0
|
| /Linux-v5.15/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 54 #define GPLL0 165
61 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
| /Linux-v5.15/drivers/clk/qcom/ |
| D | gcc-sc7180.c | 36 static struct clk_alpha_pll gpll0 = { variable
43 .name = "gpll0",
69 &gpll0.clkr.hw,
82 &gpll0.clkr.hw,
170 { .hw = &gpll0.clkr.hw },
177 { .hw = &gpll0.clkr.hw },
192 { .hw = &gpll0.clkr.hw },
209 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0.clkr.hw },
[all …]
|
| D | gcc-sm6350.c | 33 static struct clk_alpha_pll gpll0 = { variable
40 .name = "gpll0",
65 &gpll0.clkr.hw,
87 &gpll0.clkr.hw,
103 &gpll0.clkr.hw,
126 &gpll0.clkr.hw,
142 &gpll0.clkr.hw,
159 { .hw = &gpll0.clkr.hw },
192 { .hw = &gpll0.clkr.hw },
251 &gpll0.clkr.hw,
[all …]
|
| D | mmcc-msm8998.c | 56 .fw_name = "gpll0",
57 .name = "gpll0"
375 { .fw_name = "gpll0", .name = "gpll0" },
391 { .fw_name = "gpll0", .name = "gpll0" },
409 { .fw_name = "gpll0", .name = "gpll0" },
427 { .fw_name = "gpll0", .name = "gpll0" },
447 { .fw_name = "gpll0", .name = "gpll0" },
467 { .fw_name = "gpll0", .name = "gpll0" },
487 { .fw_name = "gpll0", .name = "gpll0" },
509 { .fw_name = "gpll0", .name = "gpll0" },
|
| D | gcc-sm6115.c | 56 static struct clk_alpha_pll gpll0 = { variable
65 .name = "gpll0",
89 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
121 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
478 { .hw = &gpll0.clkr.hw },
491 { .hw = &gpll0.clkr.hw },
505 { .hw = &gpll0.clkr.hw },
520 { .hw = &gpll0.clkr.hw },
535 { .hw = &gpll0.clkr.hw },
551 { .hw = &gpll0.clkr.hw },
[all …]
|
| D | gcc-sdx55.c | 37 static struct clk_alpha_pll gpll0 = { variable
46 .name = "gpll0",
74 &gpll0.clkr.hw,
145 { .hw = &gpll0.clkr.hw },
152 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
185 { .hw = &gpll0.clkr.hw },
213 { .hw = &gpll0.clkr.hw },
1568 [GPLL0] = &gpll0.clkr,
|
| D | gcc-mdm9607.c | 55 static struct clk_alpha_pll_postdiv gpll0 = { variable
60 .name = "gpll0",
74 { .hw = &gpll0.clkr.hw },
115 { .hw = &gpll0.clkr.hw },
158 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0.clkr.hw },
233 { .hw = &gpll0.clkr.hw },
1478 [GPLL0] = &gpll0.clkr,
1605 /* Vote for GPLL0 to turn on. Needed by acpuclock. */ in gcc_mdm9607_probe()
|
| D | gcc-msm8953.c | 70 static struct clk_alpha_pll_postdiv gpll0 = { variable
74 .name = "gpll0",
244 { .hw = &gpll0.clkr.hw },
256 { .hw = &gpll0.clkr.hw },
679 { .hw = &gpll0.clkr.hw },
749 { .hw = &gpll0.clkr.hw },
784 { .hw = &gpll0.clkr.hw },
850 { .hw = &gpll0.clkr.hw },
913 { .hw = &gpll0.clkr.hw },
1020 { .hw = &gpll0.clkr.hw },
[all …]
|
| D | gcc-sdm660.c | 83 static struct clk_alpha_pll_postdiv gpll0 = { variable
87 .name = "gpll0",
178 { .hw = &gpll0.clkr.hw },
189 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll0.clkr.hw },
237 { .hw = &gpll0.clkr.hw },
253 { .hw = &gpll0.clkr.hw },
267 { .hw = &gpll0.clkr.hw },
1606 &gpll0.clkr.hw,
1672 &gpll0.clkr.hw,
[all …]
|
| D | gcc-sdm845.c | 37 static struct clk_alpha_pll gpll0 = { variable
44 .name = "gpll0",
89 &gpll0.clkr.hw,
104 { .hw = &gpll0.clkr.hw },
117 { .hw = &gpll0.clkr.hw },
139 { .hw = &gpll0.clkr.hw },
159 { .hw = &gpll0.clkr.hw },
166 { .hw = &gpll0.clkr.hw },
173 { .hw = &gpll0.clkr.hw },
179 { .hw = &gpll0.clkr.hw },
[all …]
|
| D | gcc-ipq6018.c | 82 static struct clk_alpha_pll_postdiv gpll0 = { variable
87 .name = "gpll0",
98 { .hw = &gpll0.clkr.hw},
294 { .hw = &gpll0.clkr.hw },
373 { .hw = &gpll0.clkr.hw },
426 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
632 { .hw = &gpll0.clkr.hw },
666 { .hw = &gpll0.clkr.hw },
911 { .hw = &gpll0.clkr.hw },
[all …]
|
| D | gcc-ipq8074.c | 53 "gpll0",
65 "gpll0",
75 "gpll0",
89 "gpll0",
102 "gpll0",
116 "gpll0",
167 "gpll0",
181 "gpll0",
196 "gpll0",
210 "gpll0",
[all …]
|
| D | gpucc-msm8998.c | 102 { .fw_name = "gpll0", .name = "gpll0" },
|
| D | gcc-sm8250.c | 35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
67 &gpll0.clkr.hw,
116 { .hw = &gpll0.clkr.hw },
122 { .hw = &gpll0.clkr.hw },
135 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
183 { .hw = &gpll0.clkr.hw },
1394 &gpll0.clkr.hw,
1534 &gpll0.clkr.hw,
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 16 Definition: clock handle for XO clock and GPLL0 clock.
167 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
| /Linux-v5.15/include/dt-bindings/clock/ |
| D | qcom,gcc-mdm9607.h | 9 #define GPLL0 0 macro
|
| D | qcom,gcc-sdx55.h | 10 #define GPLL0 3 macro
|
| D | qcom,gcc-sc7180.h | 11 #define GPLL0 1 macro
|
