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/Linux-v5.15/arch/arm/boot/dts/
Dnuvoton-npcm750-runbmc-olympus.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 #include "nuvoton-npcm750.dtsi"
7 #include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi"
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/gpio/gpio.h>
43 stdout-path = &serial3;
50 iio-hwmon {
51 compatible = "iio-hwmon";
52 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
[all …]
Daspeed-bmc-lenovo-hr855xg2.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-present Lenovo
8 /dts-v1/;
10 #include "aspeed-g5.dtsi"
11 #include <dt-bindings/gpio/aspeed-gpio.h>
15 compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500";
29 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
[all …]
Daspeed-bmc-opp-palmetto.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
26 no-map;
[all …]
Daspeed-bmc-lenovo-hr630.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-present Lenovo
8 /dts-v1/;
10 #include "aspeed-g5.dtsi"
11 #include <dt-bindings/gpio/aspeed-gpio.h>
15 compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
29 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
[all …]
Darmada-388-clearfog.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
[all …]
Dimx6q-bx50v3.dtsi5 * This file is dual-licensed: you can use it either under the terms
43 #include "imx6q-ba16.dtsi"
46 mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <22000000>;
52 gpio-poweroff {
53 compatible = "gpio-poweroff";
58 reg_wl18xx_vmmc: regulator-wl18xx {
59 compatible = "regulator-fixed";
[all …]
Daspeed-bmc-opp-lanyang.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "inventec,lanyang-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
[all …]
Darmada-388-helios4.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 /dts-v1/;
11 #include "armada-388.dtsi"
12 #include "armada-38x-solidrun-microsom.dtsi"
25 /* So that mvebu u-boot can update the MAC addresses */
30 stdout-path = "serial0:115200n8";
33 reg_12v: regulator-12v {
34 compatible = "regulator-fixed";
35 regulator-name = "power_brick_12V";
36 regulator-min-microvolt = <12000000>;
[all …]
Daspeed-bmc-opp-mihawk.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
5 #include <dt-bindings/leds/leds-pca955x.h>
9 compatible = "ibm,mihawk-bmc", "aspeed,ast2500";
59 stdout-path = &uart5;
67 reserved-memory {
68 #address-cells = <1>;
69 #size-cells = <1>;
[all …]
Darmada-388-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-388-clearfog.dtsi"
13 compatible = "solidrun,clearfog-a1", "marvell,armada388",
17 internal-regs {
27 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-0 = <&rear_button_pins>;
36 pinctrl-names = "default";
[all …]
Dam335x-bonegreen-wireless.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "am335x-bone-common.dtsi"
9 #include "am335x-bonegreen-common.dtsi"
10 #include <dt-bindings/interrupt-controller/irq.h>
14 …compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,…
17 compatible = "regulator-fixed";
18 regulator-name = "wlan-en-regulator";
19 regulator-min-microvolt = <1800000>;
[all …]
Daspeed-bmc-opp-nicole.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "yadro,nicole-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
26 no-map;
[all …]
Dstm32mp15xx-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
17 stdout-path = "serial0:115200n8";
32 * GPIO line, however the STM32 UART driver assumes RX happens
36 rs485-rx-en-hog {
37 gpio-hog;
39 output-low;
40 line-name = "rs485-rx-en";
45 gpio-line-names = "", "", "", "",
[all …]
Dda850-lego-ev3.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/linux-event-codes.h>
11 #include <dt-bindings/pwm/pwm.h>
32 compatible = "gpio-keys";
34 pinctrl-names = "default";
35 pinctrl-0 = <&button_bias>;
40 gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
46 gpios = <&gpio 102 GPIO_ACTIVE_HIGH>;
[all …]
Dste-nomadik-s8815.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik S8815 board
7 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include "ste-nomadik-stn8815.dtsi"
12 model = "Calao Systems USB-S8815";
13 compatible = "calaosystems,usb-s8815";
24 gpio3: gpio@101e7000 {
25 /* This hog will bias the MMC/SD card detect line */
26 mmcsd-gpio {
[all …]
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dpumpkin-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = "serial0:921600n8";
21 compatible = "linaro,optee-tz";
26 gpio-keys {
27 compatible = "gpio-keys";
28 input-name = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&gpio_keys_default>;
32 volume-up {
[all …]
/Linux-v5.15/arch/arm64/boot/dts/renesas/
Dulcb-kf.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 * SSI-PCM3168A
11 * aplay -D plughw:0,2 xxx.wav
12 * arecord -D plughw:0,3 xxx.wav
23 #clock-cells = <0>;
24 compatible = "gpio-mux-clock";
26 select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>;
29 snd_3p3v: regulator-snd_3p3v {
30 compatible = "regulator-fixed";
31 regulator-name = "snd-3.3v";
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/gpio/
Dgpio-pca95xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PCA95xx I2C GPIO multiplexer
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Bindings for the family of I2C GPIO multiplexers/expanders: NXP PCA95xx,
19 - exar,xra1202
20 - maxim,max7310
21 - maxim,max7312
[all …]
Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
10 - Maxime Ripard <mripard@kernel.org>
15 - fairchild,74hc595
16 - nxp,74lvc594
21 gpio-controller: true
23 '#gpio-cells':
[all …]
Dfsl-imx-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX/MXC GPIO controller
10 - Anson Huang <Anson.Huang@nxp.com>
15 - enum:
16 - fsl,imx1-gpio
17 - fsl,imx21-gpio
18 - fsl,imx31-gpio
[all …]
Dti,omap-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP GPIO controller bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 The general-purpose interface combines general-purpose input/output (GPIO) banks.
14 Each GPIO banks provides up to 32 dedicated general-purpose pins with input
15 and output capabilities; interrupt generation in active mode and wake-up
21 - enum:
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mn-var-som-symphony.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2019-2020 Variscite Ltd.
7 /dts-v1/;
9 #include "imx8mn-var-som.dtsi"
12 model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
13 compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
15 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
16 compatible = "regulator-fixed";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
[all …]
Dimx8mm-var-som-symphony.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx8mm-var-som.dtsi"
11 model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
12 compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";
14 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
15 compatible = "regulator-fixed";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
18 regulator-name = "VSD_3V3";
[all …]
/Linux-v5.15/drivers/gpio/
Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * OF helpers for the GPIO API
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
15 #include <linux/gpio/consumer.h>
21 #include <linux/gpio/machine.h>
24 #include "gpiolib-of.h"
27 * of_gpio_spi_cs_get_count() - special GPIO counting for SPI
29 * @con_id: Function within the GPIO consumer
31 * Some elder GPIO controllers need special quirks. Currently we handle
32 * the Freescale and PPC GPIO controller with bindings that doesn't use the
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L combined Pin and GPIO controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
[all …]

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