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/Linux-v6.1/virt/kvm/
Dpfncache.c29 struct gfn_to_pfn_cache *gpc; in gfn_to_pfn_cache_invalidate_start() local
33 list_for_each_entry(gpc, &kvm->gpc_list, list) { in gfn_to_pfn_cache_invalidate_start()
34 write_lock_irq(&gpc->lock); in gfn_to_pfn_cache_invalidate_start()
37 if (gpc->valid && !is_error_noslot_pfn(gpc->pfn) && in gfn_to_pfn_cache_invalidate_start()
38 gpc->uhva >= start && gpc->uhva < end) { in gfn_to_pfn_cache_invalidate_start()
39 gpc->valid = false; in gfn_to_pfn_cache_invalidate_start()
45 if (gpc->usage & KVM_GUEST_USES_PFN) { in gfn_to_pfn_cache_invalidate_start()
50 __set_bit(gpc->vcpu->vcpu_idx, vcpu_bitmap); in gfn_to_pfn_cache_invalidate_start()
53 write_unlock_irq(&gpc->lock); in gfn_to_pfn_cache_invalidate_start()
79 bool kvm_gfn_to_pfn_cache_check(struct kvm *kvm, struct gfn_to_pfn_cache *gpc, in kvm_gfn_to_pfn_cache_check() argument
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/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgv100.c28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_gr_trap_sm() argument
32 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); in gv100_gr_trap_sm()
33 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); in gv100_gr_trap_sm()
40 nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: " in gv100_gr_trap_sm()
42 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); in gv100_gr_trap_sm()
44 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); in gv100_gr_trap_sm()
45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); in gv100_gr_trap_sm()
49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_trap_mp() argument
51 gv100_gr_trap_sm(gr, gpc, tpc, 0); in gv100_gr_trap_mp()
52 gv100_gr_trap_sm(gr, gpc, tpc, 1); in gv100_gr_trap_mp()
[all …]
Dctxgp100.c56 int gpc, ppc, b, n = 0; in gp100_grctx_generate_attrib() local
58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib()
59 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp100_grctx_generate_attrib()
72 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
73 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp100_grctx_generate_attrib()
74 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
77 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
78 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
86 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
104 const u8 gpc = gr->sm[sm].gpc; in gp100_grctx_generate_smid_config() local
[all …]
Dctxgp102.c52 int gpc, ppc, b, n = 0; in gp102_grctx_generate_attrib() local
54 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib()
55 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp102_grctx_generate_attrib()
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
69 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp102_grctx_generate_attrib()
70 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
74 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
75 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
76 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
85 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
Dctxgm200.c55 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config() local
57 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gm200_grctx_generate_smid_config()
58 gpcs[gpc] |= sm << (tpc * 8); in gm200_grctx_generate_smid_config()
87 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm200_grctx_generate_dist_skip_table()
90 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gm200_grctx_generate_dist_skip_table()
91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
95 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
96 ((u8 *)data)[gpc] |= ppc_tpcm; in gm200_grctx_generate_dist_skip_table()
Dgf100.c1174 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) in gf100_gr_trap_gpc_rop() argument
1181 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; in gf100_gr_trap_gpc_rop()
1182 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
1183 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
1184 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
1188 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " in gf100_gr_trap_gpc_rop()
1190 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, in gf100_gr_trap_gpc_rop()
1192 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
1235 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gf100_gr_trap_mp() argument
1239 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
[all …]
Dctxgv100.c73 int gpc, ppc, b, n = 0; in gv100_grctx_generate_attrib() local
75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gv100_grctx_generate_attrib()
76 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gv100_grctx_generate_attrib()
88 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
89 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gv100_grctx_generate_attrib()
90 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
94 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
95 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
103 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
157 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_grctx_generate_sm_id() argument
[all …]
Dtu102.c43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
57 u8 bank[GPC_MAX] = {}, gpc, i, j; in tu102_gr_init_zcull() local
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
69 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
70 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
71 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
73 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
Dgf117.c129 u8 bank[GPC_MAX] = {}, gpc, i, j; in gf117_gr_init_zcull() local
140 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_gr_init_zcull()
141 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf117_gr_init_zcull()
142 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf117_gr_init_zcull()
143 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf117_gr_init_zcull()
145 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf117_gr_init_zcull()
Dctxgf117.c257 int gpc, ppc; in gf117_grctx_generate_attrib() local
264 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_grctx_generate_attrib()
265 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gf117_grctx_generate_attrib()
266 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
267 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
269 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
270 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
274 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
276 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
Dgp102.c89 u32 mask = 0, data, gpc; in gp102_gr_init_swdx_pes_mask() local
91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_gr_init_swdx_pes_mask()
92 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; in gp102_gr_init_swdx_pes_mask()
93 mask |= data << (gpc * 4); in gp102_gr_init_swdx_pes_mask()
Dctxgf100.c1072 int gpc, tpc; in gf100_grctx_generate_attrib() local
1079 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1080 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_grctx_generate_attrib()
1081 const u32 o = TPC_UNIT(gpc, tpc, 0x0520); in gf100_grctx_generate_attrib()
1106 data |= gr->sm[sm++].gpc << (j * 8); in gf100_grctx_generate_r4060a8()
1275 int i, gpc; in gf100_grctx_generate_alpha_beta_tables() local
1287 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1288 if (abits[gpc] < gr->tpc_nr[gpc]) { in gf100_grctx_generate_alpha_beta_tables()
1289 abits[gpc]++; in gf100_grctx_generate_alpha_beta_tables()
1295 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
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/Linux-v6.1/Documentation/devicetree/bindings/power/
Dfsl,imx-gpcv2.yaml13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
16 Power domains contained within GPC node are generic power domain
27 - fsl,imx7d-gpc
28 - fsl,imx8mn-gpc
29 - fsl,imx8mq-gpc
30 - fsl,imx8mm-gpc
31 - fsl,imx8mp-gpc
68 include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
69 include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
70 include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
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Dfsl,imx-gpc.yaml4 $id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
13 The i.MX6 General Power Control (GPC) block contains DVFS load tracking
18 described as subnodes of the power gating controller 'pgc' node of the GPC.
27 - fsl,imx6q-gpc
28 - fsl,imx6qp-gpc
29 - fsl,imx6sl-gpc
30 - fsl,imx6sx-gpc
110 gpc@20dc000 {
111 compatible = "fsl,imx6q-gpc";
/Linux-v6.1/arch/x86/kvm/
Dxen.c35 struct gfn_to_pfn_cache *gpc = &kvm->arch.xen.shinfo_cache; in kvm_xen_shared_info_init() local
45 kvm_gpc_deactivate(kvm, gpc); in kvm_xen_shared_info_init()
50 ret = kvm_gpc_activate(kvm, gpc, NULL, KVM_HOST_USES_PFN, gpa, in kvm_xen_shared_info_init()
62 read_lock_irq(&gpc->lock); in kvm_xen_shared_info_init()
64 if (gpc->valid) in kvm_xen_shared_info_init()
67 read_unlock_irq(&gpc->lock); in kvm_xen_shared_info_init()
81 struct shared_info *shinfo = gpc->khva; in kvm_xen_shared_info_init()
88 struct compat_shared_info *shinfo = gpc->khva; in kvm_xen_shared_info_init()
104 read_unlock_irq(&gpc->lock); in kvm_xen_shared_info_init()
204 struct gfn_to_pfn_cache *gpc = &vx->runstate_cache; in kvm_xen_update_runstate_guest() local
[all …]
/Linux-v6.1/arch/mips/boot/dts/ingenic/
Dqi_lb60.dts114 col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
115 <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
186 sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>;
187 mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>;
188 cs-gpios = <&gpc 21 GPIO_ACTIVE_LOW>;
196 status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>;
Drs90.dts59 gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
65 gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
83 gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
89 gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
95 gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
128 enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
236 cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
266 rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
Dcu1000-neo.dts37 reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
72 cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
87 interrupt-parent = <&gpc>;
146 interrupt-parent = <&gpc>;
163 snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
/Linux-v6.1/drivers/irqchip/
Dirq-imx-gpcv2.c197 { .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 },
198 { .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
238 pr_err("%pOF: unable to map gpc registers\n", node); in imx_gpcv2_irqchip_init()
268 /* Let CORE0 as the default CPU to wake up by GPC */ in imx_gpcv2_irqchip_init()
283 * later the GPC power domain driver will not be skipped. in imx_gpcv2_irqchip_init()
289 IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
290 IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);
/Linux-v6.1/arch/arm/boot/dts/
Ds3c64xx-pinctrl.dtsi33 gpc: gpc-gpio-bank { label
214 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pins = "gpc-3";
226 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pins = "gpc-7";
305 samsung,pins = "gpc-4";
311 samsung,pins = "gpc-5";
354 samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
/Linux-v6.1/arch/arm/mach-imx/
Dgpc.c67 /* Tell GPC to power off ARM core when suspend */ in imx_gpc_pre_suspend()
160 .name = "GPC",
262 * later the GPC power domain driver will not be skipped. in imx_gpc_init()
268 IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
274 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); in imx_gpc_check_dt()
281 /* map GPC, so that at least CPUidle and WARs keep working */ in imx_gpc_check_dt()
Dcpu-imx5.c129 u32 gpc; in imx5_pmu_init() local
151 gpc = readl_relaxed(tigerp_base + ARM_GPC); in imx5_pmu_init()
152 gpc |= DBGEN; in imx5_pmu_init()
153 writel_relaxed(gpc, tigerp_base + ARM_GPC); in imx5_pmu_init()
Dpm-imx6.c155 .gpc_compat = "fsl,imx6q-gpc",
165 .gpc_compat = "fsl,imx6q-gpc",
175 .gpc_compat = "fsl,imx6sl-gpc",
185 .gpc_compat = "fsl,imx6sll-gpc",
195 .gpc_compat = "fsl,imx6sx-gpc",
205 .gpc_compat = "fsl,imx6ul-gpc",
248 * need to mask all interrupts in GPC before in imx6_enable_rbc()
272 /* restore GPC interrupt mask settings */ in imx6_enable_rbc()
346 * 2) Software should then unmask IRQ #32 in GPC before setting CCM in imx6_set_lpm()
545 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); in imx6q_suspend_init()
[all …]
/Linux-v6.1/drivers/soc/imx/
Dimx8m-blk-ctrl.c111 /* power up upstream GPC domain */ in imx8m_blk_ctrl_power_on()
156 /* power down upstream GPC domain */ in imx8m_blk_ctrl_power_off()
277 * We use runtime PM to trigger power on/off of the upstream GPC in imx8m_blk_ctrl_probe()
353 * control the upstream GPC domains. Things happen in the right order in imx8m_blk_ctrl_suspend()
414 * allow the handshake with the GPC to progress we put the VPUs in imx8mm_vpu_power_notifier()
422 * On power up we have no software backchannel to the GPC to in imx8mm_vpu_power_notifier()
424 * bit. On power down the GPC driver waits for the handshake. in imx8mm_vpu_power_notifier()
526 * On power up we have no software backchannel to the GPC to in imx8mm_disp_power_notifier()
528 * bit. On power down the GPC driver waits for the handshake. in imx8mm_disp_power_notifier()
596 * On power up we have no software backchannel to the GPC to in imx8mn_disp_power_notifier()
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dgpc.fuc1 /* fuc microcode for gf100 PGRAPH/GPC
112 // GPC fuc initialisation, executed by triggering ucode start, will
122 // 31:0: GPC context size
158 // determine which GPC we are, setup (optional) mmio access offset
190 clear b32 $r3 // track GPC context size here
198 // calculate GPC mmio context size
367 // Set this GPC's bit in HUB_BAR, used to signal completion of various
395 // Transfer GPC context data between GPU and storage area

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