| /Linux-v6.1/Documentation/ABI/testing/ |
| D | sysfs-platform-intel-pmc | 6 The file exposes "Extended Test Mode Register 3" global
7 reset bits. The bits are used during an Intel platform
8 manufacturing process to indicate that consequent reset
9 of the platform is a "global reset". This type of reset
13 Display global reset setting bits for PMC.
15 * bit 31 - global reset is locked
16 * bit 20 - global reset is set
19 a platform "global reset" upon consequent platform reset,
21 The "global reset bit" should be locked on a production
22 system and the file is in read-only mode.
|
| /Linux-v6.1/Documentation/devicetree/bindings/reset/ |
| D | qcom,pdc-global.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PDC Global
10 - Sibi Sankar <quic_sibis@quicinc.com>
13 The bindings describes the reset-controller found on PDC-Global (Power Domain
19 - description: on SC7180 SoCs the following compatibles must be specified
21 - const: "qcom,sc7180-pdc-global"
22 - const: "qcom,sdm845-pdc-global"
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| D | intel,rcu-gw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
10 - Dilip Kota <eswara.kota@linux.intel.com>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
19 description: Reset controller registers.
22 intel,global-reset:
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/soc/fsl/ |
| D | guts.txt | 1 * Global Utilities Block
3 The global utilities block controls power management, I/O device
4 enabling, power-on-reset configuration monitoring, general-purpose
10 - compatible : Should define the compatible device type for
11 global-utilities.
13 "fsl,qoriq-device-config-1.0"
14 "fsl,qoriq-device-config-2.0"
15 "fsl,<chip>-device-config"
16 "fsl,<chip>-guts"
17 - reg : Offset and length of the register set for the device.
[all …]
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| /Linux-v6.1/drivers/net/ethernet/aquantia/atlantic/hw_atl/ |
| D | hw_atl_llh.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
19 /* set temperature sense reset */
37 /* global */
39 /* set global microprocessor semaphore */
43 /* get global microprocessor semaphore */
46 /* set global register reset disable */
49 /* set soft reset */
52 /* get soft reset */
[all …]
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| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | selftest_hangcheck.c | 1 // SPDX-License-Identifier: MIT
47 h->gt = gt; in hang_init()
49 h->ctx = kernel_context(gt->i915, NULL); in hang_init()
50 if (IS_ERR(h->ctx)) in hang_init()
51 return PTR_ERR(h->ctx); in hang_init()
53 GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx)); in hang_init()
55 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
56 if (IS_ERR(h->hws)) { in hang_init()
57 err = PTR_ERR(h->hws); in hang_init()
61 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
[all …]
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| D | intel_reset_types.h | 1 /* SPDX-License-Identifier: MIT */
15 * flags: Control various stages of the GPU reset
17 * #I915_RESET_BACKOFF - When we start a global reset, we need to
19 * any global resources that may be clobber by the reset (such as
22 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
23 * acquire the struct_mutex to reset an engine, we need an explicit
24 * flag to prevent two concurrent reset attempts in the same engine.
28 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
31 * aborted (with -EIO reported to userspace) if set.
33 * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | phy-stih407-usb.txt | 7 - compatible : should be "st,stih407-usb2-phy"
8 - st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl registe…
9 - resets : list of phandle and reset specifier pairs. There should be two entries, one
11 - reset-names : list of reset signal names. Should be "global" and "port"
12 See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
13 See: Documentation/devicetree/bindings/reset/reset.txt
18 compatible = "st,stih407-usb2-phy";
19 #phy-cells = <0>;
23 reset-names = "global", "port";
|
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
[all …]
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| D | qcom,gcc-qcs404.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-qcs404.h
22 const: qcom,gcc-qcs404
[all …]
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| D | qcom,gcc-ipq8074.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-ipq8074.h
22 const: qcom,gcc-ipq8074
[all …]
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| D | qcom,gcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Common bindings for Qualcomm global clock control module which supports
18 '#clock-cells':
21 '#reset-cells':
24 '#power-domain-cells':
[all …]
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| D | qcom,gcc-apq8084.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-apq8084.h
19 - dt-bindings/reset/qcom,gcc-apq8084.h
[all …]
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| D | qcom,gcc-msm8916.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8916.h
19 - dt-bindings/clock/qcom,gcc-msm8939.h
[all …]
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| D | qcom,gcc-other.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-ipq4019.h
19 - dt-bindings/clock/qcom,gcc-ipq6018.h
[all …]
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| D | qcom,gcc-msm8660.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module which supports the clocks and resets on
18 - dt-bindings/clock/qcom,gcc-msm8660.h
19 - dt-bindings/reset/qcom,gcc-msm8660.h
[all …]
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| D | qcom,gcc-ipq8064.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
10 - $ref: qcom,gcc.yaml#
13 - Ansuel Smith <ansuelsmth@gmail.com>
16 Qualcomm global clock control module which supports the clocks, resets and
20 - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
21 - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
[all …]
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
102 tristate "APQ8084 Global Clock Controller"
105 Support for the global clock controller on apq8084 devices.
138 tristate "IPQ4019 Global Clock Controller"
140 Support for the global clock controller on ipq4019 devices.
145 tristate "IPQ6018 Global Clock Controller"
147 Support for global clock controller on ipq6018 devices.
153 tristate "IPQ806x Global Clock Controller"
155 Support for the global clock controller on ipq806x devices.
168 tristate "IPQ8074 Global Clock Controller"
[all …]
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| /Linux-v6.1/drivers/phy/st/ |
| D | phy-stih407-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/reset.h>
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
65 return reset_control_deassert(phy_dev->rstport); in stih407_usb2_init_port()
73 * Only port reset is asserted, phy global reset is kept untouched in stih407_usb2_exit_port()
74 * as other ports may still be active. When all ports are in reset in stih407_usb2_exit_port()
77 * reset (like here) or global reset should be equivalent. in stih407_usb2_exit_port()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,sdx55-pcie-ep
16 - qcom,sm8450-pcie-ep
20 - description: Qualcomm-specific PARF configuration registers
21 - description: DesignWare PCIe registers
22 - description: External local bus interface registers
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx93-src.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX93 System Reset Controller
10 - Peng Fan <peng.fan@nxp.com>
13 The System Reset Controller (SRC) is responsible for the generation of
14 all the system reset signals and boot argument latching.
17 - Deals with all global system reset sources from other modules,
18 and generates global system reset.
[all …]
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| /Linux-v6.1/arch/x86/include/uapi/asm/ |
| D | debugreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 debug registers. Registers 0-3 contain the addresses we wish to trap on */
28 #define DR_STEP (0x4000) /* single-step */
33 bits - each field corresponds to one of the four debug registers,
51 that the processor will reset the bit after a task switch and the other
52 is global meaning that we have to explicitly reset the bit. With linux,
57 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
59 #define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
63 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
76 #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
|
| /Linux-v6.1/drivers/gpu/drm/i915/gt/uc/ |
| D | selftest_guc_hangcheck.c | 1 // SPDX-License-Identifier: MIT
37 struct i915_gpu_error *global = >->i915->gpu_error; in intel_hang_guc() local
43 ctx = kernel_context(gt->i915, NULL); in intel_hang_guc()
45 drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx)); in intel_hang_guc()
49 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_hang_guc()
51 ce = intel_context_create(gt->engine[BCS0]); in intel_hang_guc()
54 drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret); in intel_hang_guc()
58 engine = ce->engine; in intel_hang_guc()
59 reset_count = i915_reset_count(global); in intel_hang_guc()
61 old_beat = engine->props.heartbeat_interval_ms; in intel_hang_guc()
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| /Linux-v6.1/drivers/net/phy/ |
| D | spi_ks8995.c | 1 // SPDX-License-Identifier: GPL-2.0
26 /* ------------------------------------------------------------------------ */
31 #define KS8995_REG_GC0 0x02 /* Global Control 0 */
32 #define KS8995_REG_GC1 0x03 /* Global Control 1 */
33 #define KS8995_REG_GC2 0x04 /* Global Control 2 */
34 #define KS8995_REG_GC3 0x05 /* Global Control 3 */
35 #define KS8995_REG_GC4 0x06 /* Global Control 4 */
36 #define KS8995_REG_GC5 0x07 /* Global Control 5 */
37 #define KS8995_REG_GC6 0x08 /* Global Control 6 */
38 #define KS8995_REG_GC7 0x09 /* Global Control 7 */
[all …]
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| /Linux-v6.1/Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
6 Read/Write PMU global general storage register value,
8 Global general storage register that can be used
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
32 Read/Write PMU persistent global general storage register
[all …]
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