| /Linux-v6.1/include/dt-bindings/clock/ |
| D | tegra234-clock.h | 207 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
209 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
221 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
225 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
227 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
237 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
241 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
243 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
253 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
257 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
[all …]
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| /Linux-v6.1/drivers/cpuidle/ |
| D | cpuidle-cps.c | 18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
86 .name = "clock-gated",
87 .desc = "core clock gated",
94 .name = "power-gated",
95 .desc = "core power gated",
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| /Linux-v6.1/drivers/gpu/drm/radeon/ |
| D | vce_v2_0.c | 39 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_sw_cg() argument
43 if (gated) { in vce_v2_0_set_sw_cg()
74 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_dyn_cg() argument
80 if (gated) { in vce_v2_0_set_dyn_cg()
99 if (gated) in vce_v2_0_set_dyn_cg()
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| /Linux-v6.1/sound/pci/hda/ |
| D | hda_jack.c | 214 /* If a jack is gated by this one update it. */ in jack_detect_update()
216 struct hda_jack_tbl *gated = in jack_detect_update() local
219 if (gated) { in jack_detect_update()
220 gated->jack_dirty = 1; in jack_detect_update()
221 jack_detect_update(codec, gated); in jack_detect_update()
378 * @gated_nid: gated pin NID
381 * Indicates the gated jack is only valid when the gating jack is plugged.
386 struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid, 0); in snd_hda_jack_set_gating_jack() local
392 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
395 gated->gating_jack = gating_nid; in snd_hda_jack_set_gating_jack()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.txt | 21 between gated clocks and other clocks and an index specifying the clock to
37 Specifying gated clocks
57 /* Gated clock, AHB1 bit 0 (GPIOA) */
62 /* Gated clock, AHB2 bit 4 (CRYP) */
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| D | maxim,max77686.txt | 11 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
16 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
20 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
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| D | maxim,max9485.txt | 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
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| D | brcm,bcm63xx-clocks.txt | 1 Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
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| /Linux-v6.1/arch/mips/bcm63xx/ |
| D | clk.c | 423 /* gated clocks */
441 /* gated clocks */
453 /* gated clocks */
467 /* gated clocks */
481 /* gated clocks */
497 /* gated clocks */
517 /* gated clocks */
532 /* gated clocks */
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | clock.json | 7 "PublicDescription": "FSU clocking gated off cycle",
10 "BriefDescription": "FSU clocking gated off cycle"
|
| /Linux-v6.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v12_0_ppsmc.h | 42 #define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default
44 #define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default
46 #define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default
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| D | smu_v13_0_4_ppsmc.h | 60 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by defau…
90 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by defa…
98 #define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default
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| D | smu_v13_0_5_ppsmc.h | 41 #define PPSMC_MSG_PowerUpVcn 6 ///< Power up VCN; VCN is power gated by default
54 #define PPSMC_MSG_PowerUpJpeg 19 ///< Power up Jpeg; VCN is power gated by default
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| D | smu_v11_5_ppsmc.h | 40 #define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
42 #define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
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| D | smu_v13_0_1_ppsmc.h | 51 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by defau…
78 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by defa…
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| /Linux-v6.1/drivers/staging/media/atomisp/pci/ |
| D | atomisp-regs.h | 64 * If cleared, the high speed clock going to the digital logic is gated when
65 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
66 * If this bit is set, then the high speed clock is not gated during the
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| /Linux-v6.1/arch/mips/include/asm/ |
| D | pm-cps.h | 26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
|
| /Linux-v6.1/arch/arm/mach-tegra/ |
| D | platsmp.c | 50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
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| /Linux-v6.1/Documentation/devicetree/bindings/power/ |
| D | apple,pmgr-pwrstate.yaml | 67 0 = power gated, 4 = clock gated, 15 = on.
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| /Linux-v6.1/drivers/mmc/host/ |
| D | toshsd.h | 14 #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
22 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
23 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
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| /Linux-v6.1/drivers/clk/zynqmp/ |
| D | clk-zynqmp.h | 14 /* must be gated across rate change */
16 /* must be gated across re-parent */
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| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vce_v2_0.c | 310 static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_sw_cg() argument
314 if (gated) { in vce_v2_0_set_sw_cg()
345 static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_dyn_cg() argument
356 if (gated) { in vce_v2_0_set_dyn_cg()
379 if(gated) in vce_v2_0_set_dyn_cg()
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 26 Retention: Retention is a low power state where the core is clock gated and
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
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| /Linux-v6.1/drivers/clk/imx/ |
| D | clk-composite-7ulp.c | 127 * make sure clock is gated during clock tree initialization, in imx_ulp_clk_hw_composite()
128 * the HW ONLY allow clock parent/rate changed with clock gated, in imx_ulp_clk_hw_composite()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_hubp.c | 88 * power gated, this wait would timeout. in hubp32_phantom_hubp_post_enable()
91 * it means HUBP is gated in hubp32_phantom_hubp_post_enable()
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