| /Linux-v5.15/drivers/cpuidle/ |
| D | cpuidle-cps.c | 18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
86 .name = "clock-gated",
87 .desc = "core clock gated",
94 .name = "power-gated",
95 .desc = "core power gated",
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| /Linux-v5.15/drivers/gpu/drm/radeon/ |
| D | vce_v2_0.c | 39 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_sw_cg() argument
43 if (gated) { in vce_v2_0_set_sw_cg()
74 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_dyn_cg() argument
80 if (gated) { in vce_v2_0_set_dyn_cg()
99 if (gated) in vce_v2_0_set_dyn_cg()
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| /Linux-v5.15/sound/pci/hda/ |
| D | hda_jack.c | 203 /* If a jack is gated by this one update it. */ in jack_detect_update()
205 struct hda_jack_tbl *gated = in jack_detect_update() local
208 if (gated) { in jack_detect_update()
209 gated->jack_dirty = 1; in jack_detect_update()
210 jack_detect_update(codec, gated); in jack_detect_update()
367 * @gated_nid: gated pin NID
370 * Indicates the gated jack is only valid when the gating jack is plugged.
375 struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid, 0); in snd_hda_jack_set_gating_jack() local
381 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
384 gated->gating_jack = gating_nid; in snd_hda_jack_set_gating_jack()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.txt | 21 between gated clocks and other clocks and an index specifying the clock to
37 Specifying gated clocks
57 /* Gated clock, AHB1 bit 0 (GPIOA) */
62 /* Gated clock, AHB2 bit 4 (CRYP) */
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| D | maxim,max77686.txt | 11 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
16 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
20 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
| D | maxim,max9485.txt | 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
|
| D | brcm,bcm63xx-clocks.txt | 1 Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
|
| D | gpio-gate-clock.txt | 1 Binding for simple gpio gated clock.
|
| D | mvebu-gated-clock.txt | 1 * Gated Clock bindings for Marvell EBU SoCs
4 peripheral clocks to be gated to save some power. The clock consumer
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| /Linux-v5.15/arch/mips/bcm63xx/ |
| D | clk.c | 411 /* gated clocks */
429 /* gated clocks */
441 /* gated clocks */
455 /* gated clocks */
469 /* gated clocks */
485 /* gated clocks */
505 /* gated clocks */
520 /* gated clocks */
|
| /Linux-v5.15/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | clock.json | 7 "PublicDescription": "FSU clocking gated off cycle",
10 "BriefDescription": "FSU clocking gated off cycle"
|
| /Linux-v5.15/drivers/gpu/drm/amd/pm/inc/ |
| D | smu_v12_0_ppsmc.h | 42 #define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default
44 #define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default
46 #define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default
|
| D | smu_v11_5_ppsmc.h | 40 #define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
42 #define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
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| D | smu_v13_0_1_ppsmc.h | 51 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by defau…
78 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by defa…
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| /Linux-v5.15/arch/mips/include/asm/ |
| D | pm-cps.h | 26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
|
| /Linux-v5.15/drivers/staging/media/atomisp/pci/ |
| D | atomisp-regs.h | 64 * If cleared, the high speed clock going to the digital logic is gated when
65 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
66 * If this bit is set, then the high speed clock is not gated during the
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| /Linux-v5.15/arch/arm/mach-tegra/ |
| D | platsmp.c | 50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
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| /Linux-v5.15/drivers/mmc/host/ |
| D | toshsd.h | 14 #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
22 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
23 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
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| /Linux-v5.15/drivers/clk/zynqmp/ |
| D | clk-zynqmp.h | 14 /* must be gated across rate change */
16 /* must be gated across re-parent */
|
| /Linux-v5.15/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 26 Retention: Retention is a low power state where the core is clock gated and
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
|
| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | vce_v2_0.c | 310 static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_sw_cg() argument
314 if (gated) { in vce_v2_0_set_sw_cg()
345 static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_dyn_cg() argument
356 if (gated) { in vce_v2_0_set_dyn_cg()
379 if(gated) in vce_v2_0_set_dyn_cg()
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| /Linux-v5.15/drivers/clk/baikal-t1/ |
| D | clk-ccu-pll.c | 56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
57 * DDR controller AXI-bus clocks. If they are gated the system will be
|
| /Linux-v5.15/include/sound/ |
| D | soc-dai.h | 58 * DAI bit clocks can be gated (disabled) when the DAI is not
62 #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
66 * define GATED -> CONT. GATED will be selected if both are selected.
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| /Linux-v5.15/drivers/clk/ |
| D | clk-gpio.c | 22 * DOC: basic gpio gated clock which can be enabled and disabled
32 * struct clk_gpio - gpio gated clock
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| D | clk-gemini.c | 53 * struct gemini_data_data - Gemini gated clocks
103 * not be gated off.
337 * These are the leaf gates, at boot no clocks are gated. in gemini_clk_probe()
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