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1 // SPDX-License-Identifier: GPL-2.0+10 * phy_speed_to_str - Return a string representing the PHY link speed55 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()61 * phy_duplex_to_str - Return string describing the duplex70 return "Full"; in phy_duplex_to_str()73 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()78 * phy_rate_matching_to_str - Return a string describing the rate matching92 return "open-loop"; in phy_rate_matching_to_str()94 return "Unsupported (update phy-core.c)"; in phy_rate_matching_to_str()99 * phy_interface_num_ports - Return the number of links that can be carried by[all …]
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.04 * Module Name: utmath - Integer math support routines14 /* Structures used only for 64-bit divide */22 u64 full; member28 * Optional support for 64-bit double-precision integer multiply and shift.29 * This code is configurable and is implemented in order to support 32-bit30 * kernel environments where a 64-bit double-precision math library is not39 * PARAMETERS: multiplicand - 64-bit multiplicand40 * multiplier - 32-bit multiplier41 * out_product - Pointer to where the product is returned[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */4 * is 16 bits, but aligned on a 32 bit PCI boundary31 * two-byte words.42 * Channels 1-6 contain the coupled force data Fx through Mz. Channel43 * 7 contains the sensor's calibration data. The use of channels 8-1570 * the full scales.84 * which axes to use in computing the vectors. Each bit signifies85 * selection of a single axis. The V1x axis bit corresponds to a hex86 * value of 0x0001 and the V2z bit corresponds to a hex value of91 * calculated. Setting the changeV1 bit or the changeV2 bit will[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */12 #define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */13 #define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */14 #define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */15 #define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */16 #define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */18 #define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */19 #define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */3 * Extend a 32-bit counter to 63 bits31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter35 * a relatively short period making wrap-arounds rather frequent. This36 * is a problem when implementing sched_clock() for example, where a 64-bit37 * non-wrapping monotonic value is expected to be returned.39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in42 * memory is used to synchronize with the hardware clock half-period. When43 * the top bit of both counters (hardware and in memory) differ then the[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 The STM32 DMA is a general-purpose direct memory access controller capable of13 described in the dma.txt file, using a four-cell specifier for each17 3. A 32bit mask specifying the DMA channel configuration which are device19 -bit 9: Peripheral Increment Address22 -bit 10: Memory Increment Address25 -bit 15: Peripheral Increment Offset Size[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */3 Copyright (C) 2007-2009 STMicroelectronics Ltd23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */26 #define GMAC_INT_STATUS_PMT BIT(3)27 #define GMAC_INT_STATUS_MMCIS BIT(4)28 #define GMAC_INT_STATUS_MMCRIS BIT(5)29 #define GMAC_INT_STATUS_MMCTIS BIT(6)30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)31 #define GMAC_INT_STATUS_TSTAMP BIT(9)32 #define GMAC_INT_STATUS_LPIIS BIT(10)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */4 * This file provides wrappers with sanitizer instrumentation for atomic bit8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),17 * set_bit - Atomically set a bit in memory18 * @nr: the bit to set24 * restricted to acting on a single-word quantity.33 * clear_bit - Clears a bit in memory34 * @nr: Bit to clear46 * change_bit - Toggle a bit in memory47 * @nr: Bit to change[all …]
1 // SPDX-License-Identifier: GPL-2.0-only10 * Copyright (C) 2009-2010 Motorola, Inc.23 #include <linux/nvmem-consumer.h>28 #include <linux/mfd/motorola-cpcap.h>31 * Register bit defines for CPCAP_REG_BPEOL. Some of these seem to32 * map to MC13783UG.pdf "Table 5-19. Register 13, Power Control 0"36 #define CPCAP_REG_BPEOL_BIT_EOL9 BIT(9) /* Set for EOL irq */37 #define CPCAP_REG_BPEOL_BIT_EOL8 BIT(8) /* Set for EOL irq */38 #define CPCAP_REG_BPEOL_BIT_UNKNOWN7 BIT(7)39 #define CPCAP_REG_BPEOL_BIT_UNKNOWN6 BIT(6)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */10 #define STST BIT(7) /* Self Test in Progress */11 #define DIAGF BIT(6) /* Internal Diagnostic Failure */12 #define INIT BIT(5) /* Mailbox Initialization Required */13 #define IDLE BIT(4) /* SCSI Host Adapter Idle */14 #define CDF BIT(3) /* Command/Data Out Port Full */15 #define DF BIT(2) /* Data In Port Full */16 /* BIT(1) is reserved */17 #define INVDCMD BIT(0) /* Invalid H A Command */21 #define ANYINTR BIT(7) /* Any Interrupt */[all …]
1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)7 --------14 -----------26 -------------29 into full fledged (as far as possible) CAN interfaces.33 order to fake full-duplex operation.36 enough to implement simple request-response protocols (such as OBD II),50 -----------59 ----------------------------------68 --debug \[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */5 * mcfuart.h -- ColdFire internal UART support defines.7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */57 * Define bit flags in Mode Register 1 (MR1).60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */77 * Define bit flags in Mode Register 2 (MR2).85 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */90 * Define bit flags in Status Register (USR).[all …]
1 .. SPDX-License-Identifier: GPL-2.03 TAA - TSX Asynchronous Abort11 -------------------14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations23 ------------28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some36 -------43 hardware transactional memory support to improve performance of multi-threaded[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */27 #include <media/v4l2-subdev.h>28 #include <media/v4l2-device.h>29 #include <media/v4l2-ctrls.h>30 #include <linux/v4l2-mediabus.h>31 #include <media/media-entity.h>58 * bits 31-16: numerator, bits 15-0: denominator63 * current f-number bits definition:64 * bits 31-16: numerator, bits 15-0: denominator69 * f-number range bits definition:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Driver for PCA9685 16-channel 12-bit PWM LED controller8 * based on the pwm-twl-led.c driver59 #define LED_FULL BIT(4)60 #define MODE1_ALLCALL BIT(0)61 #define MODE1_SUB3 BIT(1)62 #define MODE1_SUB2 BIT(2)63 #define MODE1_SUB1 BIT(3)64 #define MODE1_SLEEP BIT(4)65 #define MODE2_INVRT BIT(4)[all …]
1 // SPDX-License-Identifier: GPL-2.044 # define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)144 * is the only place that we'll guarantee both "dirty bit" and "dirty data"146 * after setting dirty bit but before the data is written.151 * ring-full event. It should only be read until a sem_wait() of157 * tricky case when the ring just got full, kvm will do userspace exit due to158 * ring full. When that happens, the very last PFN is set but actually the160 * we found that the dirty ring is full, refused to continue the vcpu, and164 * bit, because it's a redundant bit, and when the write happens later the bit209 while (ret == -1 && errno == EINTR); in sem_wait_until()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */135 unsigned int full; member148 unsigned int full; member159 unsigned int full; member170 /* Deep C-state Reset */175 unsigned int full; member184 /* Call-stack Mode Supported */187 unsigned int full; member192 /* Mispredict Bit Supported */199 unsigned int full; member[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */3 * linux/mii.h: definitions for MII-compatible transceivers23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */24 #define MII_STAT1000 0x0a /* 1000BASE-T status */30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */44 #define BMCR_FULLDPLX 0x0100 /* Full duplex */55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */[all …]
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)20 * - Get an error at compile-time due to __compiletime_error, if supported by25 * - Get an error at link-time due to the call to the missing function.44 " " __SYNC(full, loongson3_war) " \n" \122 " " __SYNC(full, loongson3_war) " \n" \131 "2: " __SYNC(full, loongson3_war) " \n" \223 # include <asm-generic/cmpxchg-local.h>236 * The assembly below has to combine 32 bit values into a 64 bit in __cmpxchg64()237 * register, and split 64 bit values from one register into two. If we in __cmpxchg64()240 * most significant 32 bits of the 64 bit values we're using. In order in __cmpxchg64()[all …]
7 * SPDX-License-Identifier: GPL-2.0+12 #include <linux/clk-provider.h>30 * - all transfers are cutted in 16 words burst because the FIFO hangs on31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by33 * - CS management is dumb, and goes UP between every burst, so is really a35 * to have a CS go down over the full transfer46 #define SPICC_ENABLE BIT(0)47 #define SPICC_MODE_MASTER BIT(1)48 #define SPICC_XCH BIT(2)49 #define SPICC_SMC BIT(3)[all …]
10 Addresses scanned: none, address read from Super-I/O config space24 -----------------29 configuration for channels 1-5.30 Legal values are in the range of 0-31. Bit 0 maps to31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 133 setting a bit to 0 enables the voltage input.47 -----------49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring52 implements 5 universal input channels (UCH1-5) that can be individually60 connected to the PWM outputs of the VT1211 :-().[all …]
1 # SPDX-License-Identifier: GPL-2.0-only6 An overlay filesystem combines two filesystems - an 'upper' filesystem77 directory. This full index is used to detect overlay filesystems79 the same lower dir. The full index may incur some overhead on mount84 That is, mounting an overlay which has a full index on a kernel87 Most users should say N here and enable this feature on a case-by-96 depends on 64BIT100 inodes to a unified address space. The mapped 64bit inode numbers101 might not be compatible with applications that expect 32bit inodes.103 If compatibility with applications that expect 32bit inodes is not an
1 /* SPDX-License-Identifier: GPL-2.0 */10 #include <linux/dma-mapping.h>45 /* TMC_CTL - 0x020 */46 #define TMC_CTL_CAPT_EN BIT(0)47 /* TMC_STS - 0x00C */49 #define TMC_STS_FULL BIT(0)50 #define TMC_STS_TRIGGERED BIT(1)51 #define TMC_STS_MEMERR BIT(5)53 * TMC_AXICTL - 0x11055 * TMC AXICTL format for SoC-400[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */5 * Copyright (C) 2005-2008 Nippon Telegraph and Telephone Corporation.19 #include <linux/backing-dev.h>35 * struct the_nilfs - struct to supervise multiple nilfs mount points42 * @ns_sbh: buffer heads of on-disk super blocks50 * @ns_segnum: index number of the latest full segment.51 * @ns_nextnum: index number of the full segment index to be used next52 * @ns_pseg_offset: offset of next partial segment in the current full segment68 * @ns_cptree: rb-tree of all mounted checkpoints (nilfs_root)80 * @ns_blocksize_bits: bit length of block size[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Author: David Mosberger-Tang <davidm@egauge.net>7 * (C) Copyright 2014 David Mosberger-Tang <davidm@egauge.net>9 * MAX3421 is a chip implementing a USB 2.0 Full-/Low-Speed host16 * https://www.hdl.co.jp/ftpdata/utl-001/AN3785.pdf24 * Important note on worst-case (full-speed) packet size constraints27 * - control: 64 bytes28 * - isochronous: 1023 bytes29 * - interrupt: 64 bytes30 * - bulk: 64 bytes[all …]
