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/Linux-v5.10/drivers/net/phy/
Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0+
10 * phy_speed_to_str - Return a string representing the PHY link speed
55 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()
61 * phy_duplex_to_str - Return string describing the duplex
70 return "Full"; in phy_duplex_to_str()
73 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()
79 * - iow, descending speed. */
82 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
86 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
87 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
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/Linux-v5.10/drivers/acpi/acpica/
Dutmath.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: utmath - Integer math support routines
14 /* Structures used only for 64-bit divide */
22 u64 full; member
28 * Optional support for 64-bit double-precision integer multiply and shift.
29 * This code is configurable and is implemented in order to support 32-bit
30 * kernel environments where a 64-bit double-precision math library is not
39 * PARAMETERS: multiplicand - 64-bit multiplicand
40 * multiplier - 32-bit multiplier
41 * out_product - Pointer to where the product is returned
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/Linux-v5.10/drivers/staging/comedi/drivers/
Djr3_pci.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * is 16 bits, but aligned on a 32 bit PCI boundary
31 * two-byte words.
42 * Channels 1-6 contain the coupled force data Fx through Mz. Channel
43 * 7 contains the sensor's calibration data. The use of channels 8-15
70 * the full scales.
84 * which axes to use in computing the vectors. Each bit signifies
85 * selection of a single axis. The V1x axis bit corresponds to a hex
86 * value of 0x0001 and the V2z bit corresponds to a hex value of
91 * calculated. Setting the changeV1 bit or the changeV2 bit will
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/Linux-v5.10/Documentation/devicetree/bindings/dma/
Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
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/Linux-v5.10/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
43 * the top bit of both counters (hardware and in memory) differ then the
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/Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
26 #define GMAC_INT_STATUS_PMT BIT(3)
27 #define GMAC_INT_STATUS_MMCIS BIT(4)
28 #define GMAC_INT_STATUS_MMCRIS BIT(5)
29 #define GMAC_INT_STATUS_MMCTIS BIT(6)
30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
31 #define GMAC_INT_STATUS_TSTAMP BIT(9)
32 #define GMAC_INT_STATUS_LPIIS BIT(10)
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Daltr_tse_pcs.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII BIT(1)
22 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII BIT(2)
26 #define TSE_PCS_CONTROL_AN_EN_MASK BIT(12)
28 #define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9)
34 #define TSE_PCS_STATUS_AN_COMPLETED_MASK BIT(5)
37 #define TSE_PCS_SGMII_SPEED_1000 BIT(3)
38 #define TSE_PCS_SGMII_SPEED_100 BIT(2)
46 #define TSE_PCS_PARTNER_SPEED_1000 BIT(11)
47 #define TSE_PCS_PARTNER_SPEED_100 BIT(10)
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/Linux-v5.10/include/asm-generic/bitops/
Dinstrumented-atomic.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file provides wrappers with sanitizer instrumentation for atomic bit
8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),
17 * set_bit - Atomically set a bit in memory
18 * @nr: the bit to set
24 * restricted to acting on a single-word quantity.
33 * clear_bit - Clears a bit in memory
34 * @nr: Bit to clear
46 * change_bit - Toggle a bit in memory
47 * @nr: Bit to change
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/Linux-v5.10/drivers/scsi/
Daha1542.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define STST BIT(7) /* Self Test in Progress */
11 #define DIAGF BIT(6) /* Internal Diagnostic Failure */
12 #define INIT BIT(5) /* Mailbox Initialization Required */
13 #define IDLE BIT(4) /* SCSI Host Adapter Idle */
14 #define CDF BIT(3) /* Command/Data Out Port Full */
15 #define DF BIT(2) /* Data In Port Full */
16 /* BIT(1) is reserved */
17 #define INVDCMD BIT(0) /* Invalid H A Command */
21 #define ANYINTR BIT(7) /* Any Interrupt */
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/Linux-v5.10/drivers/spi/
Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
35 * to have a CS go down over the full transfer
46 #define SPICC_ENABLE BIT(0)
47 #define SPICC_MODE_MASTER BIT(1)
48 #define SPICC_XCH BIT(2)
49 #define SPICC_SMC BIT(3)
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/Linux-v5.10/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
77 * Define bit flags in Mode Register 2 (MR2).
85 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
90 * Define bit flags in Status Register (USR).
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/Linux-v5.10/Documentation/admin-guide/hw-vuln/
Dtsx_async_abort.rst1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
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/Linux-v5.10/arch/x86/include/asm/
Dperf_event.h1 /* SPDX-License-Identifier: GPL-2.0 */
120 unsigned int full; member
133 unsigned int full; member
144 unsigned int full; member
155 /* Deep C-state Reset */
160 unsigned int full; member
169 /* Call-stack Mode Supported */
172 unsigned int full; member
177 /* Mispredict Bit Supported */
184 unsigned int full; member
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/Linux-v5.10/drivers/staging/media/atomisp/i2c/
Dov2680.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 #include <media/v4l2-subdev.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-ctrls.h>
30 #include <linux/v4l2-mediabus.h>
31 #include <media/media-entity.h>
58 * bits 31-16: numerator, bits 15-0: denominator
63 * current f-number bits definition:
64 * bits 31-16: numerator, bits 15-0: denominator
69 * f-number range bits definition:
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/Linux-v5.10/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
44 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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/Linux-v5.10/arch/mips/include/asm/
Dcmpxchg.h6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
21 * - Get an error at compile-time due to __compiletime_error, if supported by
26 * - Get an error at link-time due to the call to the missing function.
45 " " __SYNC(full, loongson3_war) " \n" \
123 " " __SYNC(full, loongson3_war) " \n" \
132 "2: " __SYNC(full, loongson3_war) " \n" \
224 # include <asm-generic/cmpxchg-local.h>
237 * The assembly below has to combine 32 bit values into a 64 bit in __cmpxchg64()
238 * register, and split 64 bit values from one register into two. If we in __cmpxchg64()
241 * most significant 32 bits of the 64 bit values we're using. In order in __cmpxchg64()
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/Linux-v5.10/fs/overlayfs/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 An overlay filesystem combines two filesystems - an 'upper' filesystem
77 directory. This full index is used to detect overlay filesystems
79 the same lower dir. The full index may incur some overhead on mount
84 That is, mounting an overlay which has a full index on a kernel
87 Most users should say N here and enable this feature on a case-by-
96 depends on 64BIT
100 inodes to a unified address space. The mapped 64bit inode numbers
101 might not be compatible with applications that expect 32bit inodes.
103 If compatibility with applications that expect 32bit inodes is not an
/Linux-v5.10/drivers/hwtracing/coresight/
Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
46 #define TMC_CTL_CAPT_EN BIT(0)
47 /* TMC_STS - 0x00C */
49 #define TMC_STS_FULL BIT(0)
50 #define TMC_STS_TRIGGERED BIT(1)
51 #define TMC_STS_MEMERR BIT(5)
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
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/Linux-v5.10/Documentation/hwmon/
Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
33 setting a bit to 0 enables the voltage input.
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
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/Linux-v5.10/drivers/iio/light/
Disl29125.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * isl29125.c - Support for Intersil ISL29125 RGB light sensor
7 * RGB light sensor with 16-bit channels for red, green, blue);
8 * 7-bit I2C slave address 0x44
10 * TODO: interrupt support, IR compensation, thresholds, 12bit
44 #define ISL29125_SENSING_RANGE_0 5722 /* 375 lux full range */
45 #define ISL29125_SENSING_RANGE_1 152590 /* 10k lux full range */
47 #define ISL29125_MODE_RANGE BIT(3)
49 #define ISL29125_STATUS_CONV BIT(1)
54 u16 buffer[8]; /* 3x 16-bit, padding, 8 bytes timestamp */
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/Linux-v5.10/fs/nilfs2/
Dthe_nilfs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * the_nilfs.h - the_nilfs shared structure.
5 * Copyright (C) 2005-2008 Nippon Telegraph and Telephone Corporation.
19 #include <linux/backing-dev.h>
35 * struct the_nilfs - struct to supervise multiple nilfs mount points
42 * @ns_sbh: buffer heads of on-disk super blocks
50 * @ns_segnum: index number of the latest full segment.
51 * @ns_nextnum: index number of the full segment index to be used next
52 * @ns_pseg_offset: offset of next partial segment in the current full segment
68 * @ns_cptree: rb-tree of all mounted checkpoints (nilfs_root)
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/Linux-v5.10/Documentation/filesystems/ext4/
Dchecksums.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
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/Linux-v5.10/drivers/usb/host/
Dmax3421-hcd.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: David Mosberger-Tang <davidm@egauge.net>
7 * (C) Copyright 2014 David Mosberger-Tang <davidm@egauge.net>
9 * MAX3421 is a chip implementing a USB 2.0 Full-/Low-Speed host
16 * https://www.hdl.co.jp/ftpdata/utl-001/AN3785.pdf
24 * Important note on worst-case (full-speed) packet size constraints
27 * - control: 64 bytes
28 * - isochronous: 1023 bytes
29 * - interrupt: 64 bytes
30 * - bulk: 64 bytes
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/Linux-v5.10/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
129 u32 full, u32 empty) in sprd_mcdt_dac_set_watermark() argument
135 water_mark |= full & MCDT_CH_FIFO_AF_MASK; in sprd_mcdt_dac_set_watermark()
141 u32 full, u32 empty) in sprd_mcdt_adc_set_watermark() argument
147 water_mark |= full & MCDT_CH_FIFO_AF_MASK; in sprd_mcdt_adc_set_watermark()
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
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/Linux-v5.10/drivers/tty/serial/
Datmel_serial.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */
17 #define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */
18 #define ATMEL_US_RXEN BIT(4) /* Receiver Enable */
19 #define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */
20 #define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */
21 #define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */
22 #define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */
23 #define ATMEL_US_STTBRK BIT(9) /* Start Break */
24 #define ATMEL_US_STPBRK BIT(10) /* Stop Break */
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