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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
/Linux-v6.1/Documentation/networking/device_drivers/ethernet/davicom/
Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
[all …]
/Linux-v6.1/arch/arm/mach-omap2/
Domap_phy_internal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file configures the internal USB PHY in OMAP4430. Used
6 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
28 * omap4430_phy_power_down: disable MUSB PHY during early init
30 * OMAP4 MUSB PHY module is enabled by default on reset, but this will
44 return -ENOMEM; in omap4430_phy_power_down()
47 /* Power down the phy */ in omap4430_phy_power_down()
79 * Start the on-chip PHY and its PLL. in am35x_musb_phy_power()
88 pr_info("Waiting for PHY clock good...\n"); in am35x_musb_phy_power()
94 pr_err("musb PHY clock good timed out\n"); in am35x_musb_phy_power()
[all …]
/Linux-v6.1/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/Linux-v6.1/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
[all …]
Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
22 stdout-path = "serial2:115200n8";
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 pmic_ap_clk: pmic-ap-clk {
34 compatible = "fixed-clock";
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/Linux-v6.1/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
44 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
[all …]
/Linux-v6.1/drivers/mmc/host/
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
94 * Force to clear BUS_TEST to in xenon_enable_sdhc()
97 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
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/Linux-v6.1/drivers/phy/allwinner/
Dphy-sun6i-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
17 #include <linux/phy/phy.h>
18 #include <linux/phy/phy-mipi-dphy.h>
21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
123 struct phy *phy; member
129 static int sun6i_dphy_init(struct phy *phy) in sun6i_dphy_init() argument
131 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init()
133 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
[all …]
/Linux-v6.1/drivers/net/phy/
Dbcm7xxx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Broadcom BCM7xxx internal transceivers support.
5 * Copyright (C) 2014-2017 Broadcom
9 #include <linux/phy.h>
11 #include "bcm-phy-lib.h"
17 /* Broadcom BCM7xxx internal PHY registers */
59 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
74 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_d0_afe_config_init()
79 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ in bcm7xxx_28nm_d0_afe_config_init()
102 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_e0_plus_afe_config_init()
[all …]
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
12 #include <linux/phy.h>
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
99 /* PHY CTRL bits */
124 /* PHY STS bits */
185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
[all …]
Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/micrel.c
9 * Copyright (c) 2010-2013 Micrel, Inc.
26 #include <linux/phy.h>
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
224 /* PHY Control 1 */
228 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
231 /* bitmap of PHY register to set interrupt mode */
393 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
397 if (type && type->interrupt_level_mask) in kszphy_config_intr()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
[all …]
/Linux-v6.1/drivers/phy/amlogic/
Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/phy/phy.h>
23 /* [31] soft reset for the phy.
44 * [3] force data byte lane in stop mode.
45 * [2] force data byte lane 0 in receiver mode.
46 * [1] write 1 to sync the txclkesc input. the internal logic have to
172 struct phy *analog;
183 static int phy_meson_axg_mipi_dphy_init(struct phy *phy) in phy_meson_axg_mipi_dphy_init() argument
185 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); in phy_meson_axg_mipi_dphy_init()
188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init()
[all …]
/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
17 #include <linux/phy.h>
27 /* General notes on dwmac-sun8i:
32 /* struct emac_variant - Describe dwmac-sun8i hardware variant
38 * @soc_has_internal_phy: Does the MAC embed an internal PHY
60 /* struct sunxi_priv_data - hold all sunxi private data
61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
[all …]
/Linux-v6.1/drivers/usb/dwc2/
Dcore.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
18 #include <linux/dma-mapping.h>
31 * dwc2_backup_global_registers() - Backup global controller registers.
41 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
44 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); in dwc2_backup_global_registers()
47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); in dwc2_backup_global_registers()
48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); in dwc2_backup_global_registers()
[all …]
/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-class-uwb_rc4 Contact: linux-usb@vger.kernel.org
9 Familiarity with the ECMA-368 'High Rate Ultra
10 Wideband MAC and PHY Specification' is assumed.
24 Contact: linux-usb@vger.kernel.org
31 Contact: linux-usb@vger.kernel.org
37 to force a specific channel to be used when beaconing,
38 or, if <channel> is -1, to prohibit beaconing. If
43 Reading returns the currently active channel, or -1 if
49 Contact: linux-usb@vger.kernel.org
52 The application-specific information element (ASIE)
[all …]
/Linux-v6.1/drivers/net/dsa/
Dbcm_sf2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/phy.h>
37 switch (priv->type) { in bcm_sf2_reg_rgmii_cntrl()
76 switch (priv->type) { in bcm_sf2_reg_led_base()
99 switch (priv->type) { in bcm_sf2_port_override_offset()
108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type); in bcm_sf2_port_override_offset()
121 for (port = 0; port < ds->num_ports; port++) { in bcm_sf2_num_active_ports()
124 if (priv->port_sts[port].enabled) in bcm_sf2_num_active_ports()
145 if (ports_active == 0 || !priv->clk_mdiv) in bcm_sf2_recalc_clock()
154 new_rate = rate_table[ports_active - 1]; in bcm_sf2_recalc_clock()
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
88 * e1000_set_phy_type - Set the phy type member in the hw struct.
93 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
94 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
96 switch (hw->phy_id) { in e1000_set_phy_type()
102 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
105 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
106 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/Linux-v6.1/include/linux/
Dbrcmphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/phy.h>
7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
8 * to configure the switch internal registers via MDIO accesses.
82 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
108 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
128 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
201 /* 01010: Auto Power-Down */
218 /* 10011: SerDes 100-FX Control Register */
220 #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
[all …]

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